Issued Patents All Time
Showing 101–125 of 160 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6791365 | Dynamic logic circuits using transistors having differing threshold voltages and delayed low threshold voltage leakage protection | — | 2004-09-14 |
| 6703884 | System and method for distributing a reference clock in an integrated circuit using filtered power supply line | — | 2004-03-09 |
| 6657484 | System and method for decoupling capacitance for an integrated circuit chip | — | 2003-12-02 |
| 6553547 | Method and system for generating charge sharing test vectors | Keerthinarayan P. Heragu | 2003-04-22 |
| 6430684 | Processor circuits, systems, and methods with efficient granularity shift and/or merge instruction(s) | — | 2002-08-06 |
| 6366941 | Multi-dimensional Galois field multiplier | Tod D. Wolf, David R. Shoemaker | 2002-04-02 |
| 6344759 | Hybrid data and clock recharging techniques in domino logic circuits minimizes charge sharing during evaluation | Pranjal Srivastava, Uming Ko | 2002-02-05 |
| 6338137 | Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer | Jonathan H. Shiell | 2002-01-08 |
| 6327218 | Integrated circuit time delay measurement apparatus | — | 2001-12-04 |
| 6304123 | Data storage circuits using a low threshold voltage output enable circuit | — | 2001-10-16 |
| 6279077 | Bus interface buffer control in a microprocessor | Mitra Nasserbakht | 2001-08-21 |
| 6261879 | Differential SOI amplifiers having tied floating body connections | Theodore W. Houston | 2001-07-17 |
| 6246266 | Dynamic logic circuits using selected transistors connected to absolute voltages and additional selected transistors connected to selectively disabled voltages | — | 2001-06-12 |
| 6242952 | Inverting hold time latch circuits, systems, and methods | Paul E. Landman | 2001-06-05 |
| 6231147 | Data storage circuits using a low threshold voltage output enable circuit | — | 2001-05-15 |
| 6223248 | Circuits systems and methods for re-mapping memory row redundancy during two cycle cache access | — | 2001-04-24 |
| 6177300 | Memory with storage cells having SOI drive and access transistors with tied floating body connections | Theodore W. Houston | 2001-01-23 |
| 6078634 | Phase-locked loop circuit with a multi-cycle phase detector and multi-current charge pump | — | 2000-06-20 |
| 6065146 | Error correcting memory | — | 2000-05-16 |
| 6055204 | Circuits, systems, and methods for re-mapping memory column redundancy | — | 2000-04-25 |
| 6049231 | Dynamic multiplexer circuits, systems, and methods having three signal inversions from input to output | — | 2000-04-11 |
| 6049672 | Microprocessor with circuits, systems, and methods for operating with patch micro-operation codes and patch microinstruction codes stored in multi-purpose memory structure | Jonathan H. Shiell | 2000-04-11 |
| 6040716 | Domino logic circuits, systems, and methods with precharge control based on completion of evaluation by the subsequent domino logic stage | — | 2000-03-21 |
| 6037808 | Differential SOI amplifiers having tied floating body connections | Theodore W. Houston | 2000-03-14 |
| 6021087 | Dynamic logic memory addressing circuits, systems, and methods with decoder fan out greater than 2:1 | — | 2000-02-01 |