Issued Patents All Time
Showing 526–550 of 865 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8112685 | Serial compressed data I/O in a parallel test compression architecture | — | 2012-02-07 |
| 8112684 | Input linking circuitry connected to test mode select and enables | Baher Haroun, Brian J. Lasher, Anjali Vij | 2012-02-07 |
| 8108742 | Tap control of TCA scan clock and scan enable | — | 2012-01-31 |
| 8099641 | Multiplexer selecting STP clock signal with tap control outputs | — | 2012-01-17 |
| 8099642 | Formatter selectively outputting scan stimulus data from scan response data | — | 2012-01-17 |
| 8094765 | Clock and mode signals controlling data communication in three states | — | 2012-01-10 |
| 8095839 | Position independent testing of circuits | — | 2012-01-10 |
| 8095838 | Transitioning through idle 1, 2 and sequence 1 machine states | — | 2012-01-10 |
| 8078927 | Wrapper leads gating TAP instruction and data registers | — | 2011-12-13 |
| 8065578 | Inverted TCK access port selector selecting one of plural TAPs | — | 2011-11-22 |
| 8065577 | Dual controllers for scan paths, distributors, and collectors | — | 2011-11-22 |
| 8055967 | TAP interface outputs connected to TAP interface inputs | — | 2011-11-08 |
| 8055962 | Testing IC functional and test circuitry having separate input/output pads | Richard L. Antley | 2011-11-08 |
| 8051351 | DDR circuit with addressable TAP linking circuitry and plural TAPS | — | 2011-11-01 |
| 8051349 | Link instruction register with instruction register, and gate and multiplexer | — | 2011-11-01 |
| 8046650 | TAP with control circuitry connected to device address port | — | 2011-10-25 |
| 8046651 | Compare circuit receiving scan register and inverted clock flip-flop data | — | 2011-10-25 |
| 8046649 | Scan circuits formed peripheral of core circuits with control leads | — | 2011-10-25 |
| 8037386 | TAP with select output from one of IR and DR | — | 2011-10-11 |
| 8037383 | Gating circuitry coupling selected scan paths between I/O scan bus | — | 2011-10-11 |
| 8028212 | Parallel scan paths with header data circuitry and header return circuitry | — | 2011-09-27 |
| 8020059 | Tap and control with data I/O, TMS, TDI, and TDO | — | 2011-09-13 |
| 8020057 | Comparator circuitry connected to input and output of tristate buffer | — | 2011-09-13 |
| 8018241 | Logic applying different bit positions to respective scan paths | — | 2011-09-13 |
| 8015463 | IC with TAP, DIO interface, SIPE, and PISO circuits | — | 2011-09-06 |