Issued Patents All Time
Showing 576–600 of 865 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7945832 | Interface to full and reduced pin JTAG devices | — | 2011-05-17 |
| 7937635 | Selectively accessing test access ports in a multiple test access port environment | — | 2011-05-03 |
| 7937637 | TAP with enable input gated and multiplexed mode select | — | 2011-05-03 |
| 7936183 | IC output signal path with switch, bus holder, and buffer | — | 2011-05-03 |
| 7925943 | Multiplexer connecting TDI or AX1/TDI to data and instruction registers | — | 2011-04-12 |
| 7925951 | Scan circuitry controlled switch connecting buffer output to test lead | — | 2011-04-12 |
| 7925946 | DDR gate and delay clock circuitry for parallel interface registers | — | 2011-04-12 |
| 7925945 | Generator/compactor scan circuit low power adapter | — | 2011-04-12 |
| 7925942 | Augmentation instruction shift register with serial and two parallel inputs | Baher Haroun | 2011-04-12 |
| 7917824 | Scan path adaptor with state machine, counter, and gate circuitry | — | 2011-03-29 |
| 7917822 | Serial I/O using JTAG TCK and TMS signals | — | 2011-03-29 |
| 7913135 | Interconnections for plural and hierarchical P1500 test wrappers | — | 2011-03-22 |
| 7908537 | Boundary scan path method and system with functional and non-functional scan cell memories | — | 2011-03-15 |
| 7904774 | Wafer scale testing using a 2 signal JTAG interface | — | 2011-03-08 |
| 7900110 | Optimized JTAG interface | — | 2011-03-01 |
| 7890829 | Reduced signaling interface method and apparatus | — | 2011-02-15 |
| 7890825 | Data summing boundary cell | — | 2011-02-15 |
| 7876112 | Parallel scan distributors and collectors and process of testing integrated circuits | — | 2011-01-25 |
| 7877651 | Dual mode test access port method and apparatus | — | 2011-01-25 |
| 7877653 | Address and TMS gating circuitry for TAP control circuit | — | 2011-01-25 |
| 7877658 | IEEE 1149.1 and P1500 test interfaces combined circuits and processes | — | 2011-01-25 |
| 7877654 | Selectable JTAG or trace access with data store and output | — | 2011-01-25 |
| 7877650 | Core circuit test architecture | — | 2011-01-25 |
| 7873889 | JTAG bus communication method and apparatus | — | 2011-01-18 |
| 7870451 | Automatable scan partitioning for low power using external control | Jayashree Saxena | 2011-01-11 |