JD

Jonathan Philip Davis

TI Texas Instruments: 11 patents #1,283 of 12,488Top 15%
IL Infineon Technologies Richmond, Lp: 4 patents #2 of 88Top 3%
Infineon Technologies Ag: 2 patents #91 of 446Top 25%
Motorola: 1 patents #6,475 of 12,470Top 55%
WP White Oak Semiconductor Partnership: 1 patents #2 of 13Top 20%
Overall (All Time): #287,997 of 4,157,543Top 7%
16
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
12159846 Process flow for fabrication of cap metal over top metal with sinter before protective dielectric etch Richard Allen Faust, Robert M. Higgins, Anagha Kulkarni, Sudtida Lavangkul, Andrew Frank Burnett 2024-12-03
11916067 High reliability polysilicon components Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang +1 more 2024-02-27
11908729 Selective etches for reducing cone formation in shallow trench isolations Karen Hildegard Ralston Kirmse 2024-02-20
11742208 Method of reducing voids and seams in trench structures by forming semi-amorphous polysilicon Damien Thomas Gilmore, Azghar H Khazi-Syed, Shariq Arshad, Khanh Quang Le, Kaneez Eshaher Banu +3 more 2023-08-29
11443879 Magnetic core for integrated magnetic devices Fuchao Wang, Yousong Zhang, Neal Murphy, Brian Zinn 2022-09-13
11296075 High reliability polysilicon components Robert M. Higgins, Henry Litzmann Edwards, Xiaoju Wu, Shariq Arshad, Li Wang +1 more 2022-04-05
11171035 Selective etches for reducing cone formation in shallow trench isolations Karen Hildegard Ralston Kirmse 2021-11-09
10453738 Selective etches for reducing cone formation in shallow trench isolations Karen Hildegard Ralston Kirmse 2019-10-22
10403424 Method to form magnetic core for integrated magnetic devices Fuchao Wang, Yousong Zhang, Neal Murphy, Brian Zinn 2019-09-03
10090264 Method to improve CMP scratch resistance for non planar surfaces Andrew Frank Burnett, Brian Zinn 2018-10-02
9604338 Method to improve CMP scratch resistance for non planar surfaces Andrew Frank Burnett, Brian Zinn 2017-03-28
7351642 Deglaze route to compensate for film non-uniformities after STI oxide processing Walter Hartner, Joseph E. Page, Jr. 2008-04-01
6927462 Method of forming a gate contact in a semiconductor device Francis Goodwin, Michael Rennie 2005-08-09
6818534 DRAM having improved leakage performance and method for making same Stephen Rusinko 2004-11-16
6472291 Planarization process to achieve improved uniformity across semiconductor wafers Joseph E. Page, Jr., Scott William Hill Bailey 2002-10-29
6174787 Silicon corner rounding by ion implantation for shallow trench isolation Robert T. Fuller, Michael Rennie 2001-01-16