| 11522118 |
Superconductor structure with normal metal connection to a resistor and method of making the same |
Christopher F. Kirby, Daniel O'Donnell, Aurelius L. Graninger, Aaron A. Pesetski |
2022-12-06 |
| 10985059 |
Preclean and dielectric deposition methodology for superconductor interconnect fabrication |
Brian Wagner, Christopher F. Kirby, James T. Kelliher, Khyhouth Lim |
2021-04-20 |
| 10763419 |
Deposition methodology for superconductor interconnects |
Christopher F. Kirby, Vivien M. Luu, Sean R. McLaughlin |
2020-09-01 |
| 10608159 |
Method of making a superconductor device |
Christopher F. Kirby, Daniel O'Donnell |
2020-03-31 |
| 10312141 |
Preclean methodology for superconductor interconnect fabrication |
Christopher F. Kirby, Sandro J. Di Giacomo |
2019-06-04 |
| 10312142 |
Method of forming superconductor structures |
Christopher F. Kirby, Daniel O'Donnell, Sandro J. Di Giacomo |
2019-06-04 |
| 10276504 |
Preclean and deposition methodology for superconductor interconnects |
Vivien M. Luu, Christopher F. Kirby, Brian Wagner |
2019-04-30 |
| 10158062 |
Superconductor device interconnect |
Christopher F. Kirby, Aurelius L. Graninger |
2018-12-18 |
| 10003005 |
Superconductor device interconnect |
Christopher F. Kirby, Aurelius L. Graninger |
2018-06-19 |
| 9812445 |
Bipolar junction transistor device having base epitaxy region on etched opening in DARC layer |
Patrick B. Shea, Sandro J. Di Giacomo |
2017-11-07 |
| 9780285 |
Superconductor device interconnect structure |
Christopher F. Kirby, Daniel O'Donnell |
2017-10-03 |
| 9142546 |
Method of making bipolar junction transistor by forming base epitaxy region on etched opening in DARC layer |
Patrick B. Shea, Sandro J. Di Giacomo |
2015-09-22 |
| 8551856 |
Embedded capacitor and method of fabricating the same |
Thomas J. Knight |
2013-10-08 |
| 8409950 |
Method for integrating SONOS non-volatile memory into a sub-90 nm standard CMOS foundry process flow |
Patrick B. Shea, Dennis A. Adams, Joseph T. Smith |
2013-04-02 |
| 7402487 |
Process for fabricating a semiconductor device having deep trench structures |
Stephen Rusinko |
2008-07-22 |
| 7208326 |
Edge protection process for semiconductor device fabrication |
Jon P Davis, Robert T. Fuller, Franz Hagl |
2007-04-24 |
| 6927462 |
Method of forming a gate contact in a semiconductor device |
Francis Goodwin, Jonathan Philip Davis |
2005-08-09 |
| 6174787 |
Silicon corner rounding by ion implantation for shallow trench isolation |
Robert T. Fuller, Jonathan Philip Davis |
2001-01-16 |