| 12260165 |
Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture |
Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran +1 more |
2025-03-25 |
| 11822376 |
Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture |
Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran +1 more |
2023-11-21 |
| 11625519 |
Systems and methods for intelligent graph-based buffer sizing for a mixed-signal integrated circuit |
Andrew Morten, Michael Siegrist, David Fick |
2023-04-11 |
| 11068641 |
Systems and methods for intelligently buffer tracking for optimized dataflow within an integrated circuit architecture |
Pei-Ci Wu, Andrew Morten, Anthony Romano, Balaji Iyer, Alexander Dang-Tran +1 more |
2021-07-20 |
| 10929748 |
Systems and methods for implementing operational transformations for restricted computations of a mixed-signal integrated circuit |
Andrew Morten, Pei-Ci Wu, Michail Tzoufras, David Fick |
2021-02-23 |
| 8549466 |
Tiered register allocation |
Dineel D. Sule, Todd T. Hahn |
2013-10-01 |
| 8213695 |
Device and software for screening the skin |
George Zouridakis, Xiaojing Yuan, Ji Chen, Yanmin Wu |
2012-07-03 |
| 7673119 |
VLIW optional fetch packet header extends instruction set space |
Michael D. Asal, Todd T. Hahn |
2010-03-02 |
| 7581082 |
Software source transfer selects instruction word sizes |
Todd T. Hahn, Michael D. Asal |
2009-08-25 |
| 7062762 |
Partitioning symmetric nodes efficiently in a split register file architecture |
Gayathri Krishnamurthy, Elana D. Granston |
2006-06-13 |
| 6892380 |
Method for software pipelining of irregular conditional control loops |
Elana D. Granston, Joseph Zbiciak |
2005-05-10 |
| 6889320 |
Microprocessor with an instruction immediately next to a branch instruction for adding a constant to a program counter |
Alan L. Davis, Richard H. Scales, Natarajan Seshan, Reid E. Tatge |
2005-05-03 |
| 6799266 |
Methods and apparatus for reducing the size of code with an exposed pipeline by encoding NOP operations as instruction operands |
Elana D. Granston, Alan Ward |
2004-09-28 |
| 6754893 |
Method for collapsing the prolog and epilog of software pipelined loops |
Elana D. Granston, Joseph Zbiciak, Alan Ward |
2004-06-22 |
| 6691240 |
System and method of implementing variabe length delay instructions, which prevents overlapping lifetime information or values in efficient way |
David Hoyle, Joseph Zbiciak |
2004-02-10 |
| 6178499 |
Interruptable multiple execution unit processing during operations utilizing multiple assignment of registers |
Richard H. Scales |
2001-01-23 |
| 5884023 |
Method for testing an integrated circuit with user definable trace function |
Gary L. Swoboda |
1999-03-16 |