PR

Paritosh Rajora

TE Tegal: 4 patents #14 of 53Top 30%
Overall (All Time): #1,266,342 of 4,157,543Top 35%
4
Patents All Time

Issued Patents All Time

Patent #TitleCo-InventorsDate
6774046 Method for minimizing the critical dimension growth of a feature on a semiconductor wafer Stephen P. DeOrnellas, Alferd Cofer, Leslie G. Jerde, Kurt A. Olson 2004-08-10
6492280 Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls Stephen P. DeOrnellas, Alferd Cofer 2002-12-10
6127277 Method and apparatus for etching a semiconductor wafer with features having vertical sidewalls Stephen P. DeOrnellas, Alferd Cofer 2000-10-03
6046116 Method for minimizing the critical dimension growth of a feature on a semiconductor wafer Stephen P. DeOrnellas, Alfred Cofer, Leslie G. Jerde, Kurt A. Olson 2000-04-04