Issued Patents All Time
Showing 26–50 of 166 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12165732 | Sense amplifier | Chia-Fu Lee, Hon-Jarn Lin | 2024-12-10 |
| 12165722 | Non-volatile memory circuit and method | Gu-Huan Li, Chen-Ming Hung | 2024-12-10 |
| 12165705 | Memory cell array circuit and method of forming the same | Chin-I Su, Chung-Cheng Chou, Zheng-Jun Lin | 2024-12-10 |
| 12165704 | Memory device with write pulse trimming | Hiroki Noguchi, Yih Wang | 2024-12-10 |
| 12164882 | In-memory computation circuit and method | Hidehiro Fujiwara, Yi-Chun Shih, Po-Hao Lee, Yen-Huei Chen, Chia-Fu Lee +1 more | 2024-12-10 |
| 12147784 | Compute in memory | Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hidehiro Fujiwara, Haruki Mori +1 more | 2024-11-19 |
| 12080375 | Circuits and methods for compensating a mismatch in a sense amplifier | Ku-Feng Lin, Yi-Chun Shih, Chia-Fu Lee | 2024-09-03 |
| 12073916 | Back-up and restoration of register data | — | 2024-08-27 |
| 12051466 | Memory cell including programmable resistors with transistor components | Jonathan Tsung-Yung Chang, Yun-Sheng Chen, Maybe Chen, Ya-Chin King, Wen-Zhang Lin +2 more | 2024-07-30 |
| 12041860 | Resistive memory device and method for manufacturing with protrusion of electrode | Wen-Zhang Lin, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Chrong-Jung Lin, Ya-Chin King +2 more | 2024-07-16 |
| 12027205 | Resistive memory with low voltage operation | Zheng-Jun Lin, Chung-Cheng Chou | 2024-07-02 |
| 12026404 | Memory device for scheduling maximum number of memory macros write operations at re-arranged time intervals | Hiroki Noguchi, Shih-Lien Linus Lu, Yih Wang | 2024-07-02 |
| 12009029 | System and method applied with computing-in-memory | Meng-Fan Chang, May-Be Chen, Cheng Xue, Je Syu Liu | 2024-06-11 |
| 11984162 | Hybrid self-tracking reference circuit for RRAM cells | Zheng-Jun Lin, Chung-Cheng Chou, Pei-Ling Tseng | 2024-05-14 |
| 11978518 | Sense amplifier control | Chung-Chieh Chen, Cheng-Hsiung Kuo | 2024-05-07 |
| 11973502 | Latch | Chia-Fu Lee, Hon-Jarn Lin | 2024-04-30 |
| 11962693 | Integrated circuit (IC) signatures with random number generator and one-time programmable device | Shih-Lien Linus Lu, Kun-Hsi Li, Shih-Liang Wang, Jonathan Tsung-Yung Chang, Cheng-En Lee | 2024-04-16 |
| 11961546 | MRAM reference current | Chia-Fu Lee, Hon-Jarn Lin, Po-Hao Lee, Ku-Feng Lin, Yi-Chun Shih | 2024-04-16 |
| 11943936 | Semiconductor device and method of manufacturing the same | May-Be Chen, Yun-Sheng Chen, Jonathan Tsung-Yung Chang, Wen-Zhang Lin, Chrong-Jung Lin +3 more | 2024-03-26 |
| 11922108 | Method of forming a memory cell array circuit | Chi-Hsiang Weng | 2024-03-05 |
| 11923036 | Memory sense amplifier trimming | Yi-Chun Shih, Chia-Fu Lee | 2024-03-05 |
| 11915754 | Resistive random access memory device | Chung-Cheng Chou, Wen-Ting Chu | 2024-02-27 |
| 11915752 | Resistive memory with enhanced redundancy writing | Chung-Cheng Chou, Chun-Yun Wu, Chen-Ming Hung | 2024-02-27 |
| 11848040 | Memory device and reference circuit thereof | Chia-Fu Lee, Hon-Jarn Lin, Yi-Chun Shih | 2023-12-19 |
| 11797831 | Method and apparatus for defect-tolerant memory based artificial neural network | Win-San Khwa, Yi-Chun Shih, Chien-Yin Liu | 2023-10-24 |