Issued Patents All Time
Showing 26–50 of 102 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8236658 | Methods for forming a transistor with a strained channel | Ta-Ming Kuan, Chih-Hsin Ko | 2012-08-07 |
| 8211267 | Electromagnetic shielding composite and method for making the same | Cheng-Hsien Lin, Yao-Wen Bai, Rui Zhang, Kai-Li Jiang, Chen Feng | 2012-07-03 |
| 8154107 | Semiconductor device and a method of fabricating the device | Chung-Hu Ke, Chih-Hsin Ko | 2012-04-10 |
| 8101266 | Multilayer printed circuit board | Cheng-Hsien Lin | 2012-01-24 |
| 8089003 | Printed circuit board assembly | Cheng-Hsien Lin | 2012-01-03 |
| 8084305 | Isolation spacer for thin SOI devices | Chih-Hsin Ko, Yee-Chia Yeo, Chung-Hu Ke | 2011-12-27 |
| 8062946 | Strained channel transistor structure with lattice-mismatched zone and fabrication method thereof | Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu | 2011-11-22 |
| 8039284 | Dual metal silicides for lowering contact resistance | Chung-Hu Ke, Chih-Hsin Ko, Hung-Wei Chen | 2011-10-18 |
| 8030210 | Contact barrier structure and manufacturing methods | Ching-Ya Wang, Chung-Hu Ke | 2011-10-04 |
| 7987586 | Method for manufacturing printed circuit board having different thicknesses in different areas | Dong He, Ming Wang, Yun Zhu | 2011-08-02 |
| 7985652 | Metal stress memorization technology | Chung-Hu Ke, Ta-Ming Kuan, Chih-Hsin Ko | 2011-07-26 |
| 7928474 | Forming embedded dielectric layers adjacent to sidewalls of shallow trench isolation regions | Hong-Nien Lin, Chih-Hsin Ko | 2011-04-19 |
| 7875959 | Semiconductor structure having selective silicide-induced stress and a method of producing same | Chung-Hu Ke, Chenming Hu | 2011-01-25 |
| 7839647 | Insulating film, printed circuit board substrate and printed circuit board including same | Cheng-Hsien Lin | 2010-11-23 |
| 7834345 | Tunnel field-effect transistors with superlattice channels | Krishna Kumar Bhuwalka, Ching-Ya Wang, Ken-Ichi Goto, Carlos H. Diaz | 2010-11-16 |
| 7807546 | SRAM cell having stepped boundary regions and methods of fabrication | Yee-Chia Yeo | 2010-10-05 |
| 7803718 | BiCMOS performance enhancement by mechanical uniaxial strain and methods of manufacture | Chih-Hsin Ko, Tzu-Juei Wang, Hung-Wei Chen, Chung-Hu Ke | 2010-09-28 |
| 7758716 | Apparatus for spraying etchant solution onto preformed printed circuit board | Cheng-Hsien Lin | 2010-07-20 |
| 7737532 | Hybrid Schottky source-drain CMOS for high mobility and low barrier | Chung-Hu Ke, Chih-Hsin Ko, Hung-Wei Chen, Min-hwa Chi | 2010-06-15 |
| 7709903 | Contact barrier structure and manufacturing methods | Ching-Ya Wang, Chung-Hu Ke | 2010-05-04 |
| 7667247 | Method for passivating gate dielectric films | Ching-Ya Wang, Denny Tang | 2010-02-23 |
| 7646068 | Structure and method of a strained channel transistor and a second semiconductor component in an integrated circuit | Chih-Hsin Ko, Yee-Chia Yeo, Chun-Chieh Lin, Chenming Hu | 2010-01-12 |
| 7592619 | Epitaxy layer and method of forming the same | Pang-Yen Tsai, Liang-Gi Yao, Chun-Chieh Lin, Shih-Chang Chen | 2009-09-22 |
| 7582934 | Isolation spacer for thin SOI devices | Chih-Hsin Ko, Yee-Chia Yeo, Chung-Hu Ke | 2009-09-01 |
| 7569896 | Transistors with stressed channels | Chih-Hsin Ko, Chung-Hu Ke, Hung-Wei Chen | 2009-08-04 |