Issued Patents All Time
Showing 26–50 of 70 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11848207 | Method and structure of cut end with self-aligned double patterning | Hsi-Wen Tien, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2023-12-19 |
| 11842924 | Dual etch-stop layer structure | Hsi-Wen Tien, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee | 2023-12-12 |
| 11842966 | Integrated chip with inter-wire cavities | Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai +2 more | 2023-12-12 |
| 11837546 | Self-aligned cavity strucutre | Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai | 2023-12-05 |
| 11798910 | Self-aligned interconnect structure | Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai | 2023-10-24 |
| 11798840 | Self-assembled dielectric on metal RIE lines to increase reliability | Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee | 2023-10-24 |
| 11776845 | Semiconductor arrangement and method of making | Hsi-Wen Tien, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2023-10-03 |
| 11756884 | Interconnection structure and methods of forming the same | Hsi-Wen Tien, Yu-Teng Dai, Chih Wei Lu, Hsin-Chieh Yao, Chung-Ju Lee | 2023-09-12 |
| 11723282 | Magneto-resistive random-access memory (MRAM) devices with self-aligned top electrode via | Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee | 2023-08-08 |
| 11688782 | Semiconductor structure and method for forming the same | Hsi-Wen Tien, Chih Wei Lu, Yu-Teng Dai, Hsin-Chieh Yao, Chung-Ju Lee | 2023-06-27 |
| 11652054 | Dielectric on wire structure to increase processing window for overlying via | Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai | 2023-05-16 |
| 11569127 | Double patterning approach by direct metal etch | Hsi-Wen Tien, Yu-Teng Dai, Hsin-Chieh Yao, Chih Wei Lu, Chung-Ju Lee | 2023-01-31 |
| 11569096 | Semiconductor device | Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee | 2023-01-31 |
| 11563167 | Structure and method for an MRAM device with a multi-layer top electrode | Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee | 2023-01-24 |
| 11521896 | Selective deposition of a protective layer to reduce interconnect structure critical dimensions | Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Yu-Teng Dai | 2022-12-06 |
| 11488926 | Self-aligned interconnect structure | Hsin-Chieh Yao, Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai | 2022-11-01 |
| 11482447 | Method of forming an integrated chip having a cavity between metal features | Hsi-Wen Tien, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Shau-Lin Shue +1 more | 2022-10-25 |
| 11362030 | Sidewall spacer structure enclosing conductive wire sidewalls to increase reliability | Yu-Teng Dai, Chung-Ju Lee, Chih Wei Lu, Hsin-Chieh Yao, Hsi-Wen Tien | 2022-06-14 |
| 11355701 | Integrated circuit | Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee | 2022-06-07 |
| 11329216 | Magnetic tunnel junction devices | Hsi-Wen Tien, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2022-05-10 |
| 11302641 | Self-aligned cavity strucutre | Chung-Ju Lee, Chih Wei Lu, Hsi-Wen Tien, Yu-Teng Dai | 2022-04-12 |
| 11189524 | Semiconductor arrangement and method of making | Hsi-Wen Tien, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2021-11-30 |
| 11171284 | Memory device | Chih Wei Lu, Hsi-Wen Tien, Pin-Ren Dai, Chung-Ju Lee | 2021-11-09 |
| 11171052 | Methods of forming interconnect structures with selectively deposited pillars and structures formed thereby | Hsi-Wen Tien, Pin-Ren Dai, Chih Wei Lu, Chung-Ju Lee | 2021-11-09 |
| 11158518 | Methods of etching metals in semiconductor devices | Hsi-Wen Tien, Chih Wei Lu, Pin-Ren Dai, Chung-Ju Lee | 2021-10-26 |