Issued Patents All Time
Showing 76–86 of 86 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9640431 | Method for via plating with seed layer | Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming-Han Lee | 2017-05-02 |
| 9613854 | Method and apparatus for back end of line semiconductor device processing | Hsiang-Huan Lee, Ming-Han Lee, Ching-Fu Yeh, Pei-Yin Liou | 2017-04-04 |
| 9613856 | Method of forming metal interconnection | Ming-Han Lee, Shau-Lin Shue, Tz-Jun Kuo | 2017-04-04 |
| 9496170 | Interconnect having air gaps and polymer wrapped conductive lines | Hsiang-Huan Lee, Ming-Han Lee, Hsi-Wen Tien, Shau-Lin Shue | 2016-11-15 |
| 9484302 | Semiconductor devices and methods of manufacture thereof | Ming-Han Lee, Hsiang-Huan Lee, Hsien-Chang Wu | 2016-11-01 |
| 9324608 | Method for via plating with seed layer | Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming-Han Lee | 2016-04-26 |
| 9318439 | Interconnect structure and manufacturing method thereof | Hsi-Wen Tien, Ming-Han Lee, Hsiang-Huan Lee, Shau-Lin Shue | 2016-04-19 |
| 9269668 | Interconnect having air gaps and polymer wrapped conductive lines | Hsiang-Huan Lee, Ming-Han Lee, Hsi-Wen Tien, Shau-Lin Shue | 2016-02-23 |
| 9142505 | Method and apparatus for back end of line semiconductor device processing | Hsiang-Huan Lee, Ming-Han Lee, Ching-Fu Yeh, Pei-Yin Liou | 2015-09-22 |
| 9054163 | Method for via plating with seed layer | Ching-Fu Yeh, Tz-Jun Kuo, Hsiang-Huan Lee, Ming-Han Lee | 2015-06-09 |
| 9006095 | Semiconductor devices and methods of manufacture thereof | Ming-Han Lee, Hsiang-Huan Lee, Hsien-Chang Wu | 2015-04-14 |