Issued Patents All Time
Showing 151–175 of 232 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11342325 | Integration of multiple fin structures on a single substrate | Chih-Chao Chou, Chih-Hao Wang, Kuo-Cheng Chiang, Wen-Ting Lan | 2022-05-24 |
| 11329165 | Structure and formation method of semiconductor device with isolation structure | Kuo-Cheng Chiang, Huan-Chieh Su, Kuan-Ting Pan, Chih-Hao Wang | 2022-05-10 |
| 11328963 | Multi-gate device and related methods | Kuan-Ting Pan, Huan-Chieh Su, Zhi-Chang Lin, Yi-Ruei Jhan, Kuo-Cheng Chiang +1 more | 2022-05-10 |
| 11315925 | Uniform gate width for nanostructure devices | Jui-Chien Huang, Shih-Cheng Chen, Chih-Hao Wang, Kuo-Cheng Chiang, Zhi-Chang Lin +3 more | 2022-04-26 |
| 11302580 | Nanosheet thickness | Wen-Ting Lan, Kuan-Ting Pan, Kuo-Cheng Chiang, Chih-Hao Wang | 2022-04-12 |
| 11302825 | Self-aligned spacers for multi-gate devices and method of fabrication thereof | Kuo-Cheng Ching, Guan-Lin Chen, Kuan-Lun Cheng, Chih-Hao Wang | 2022-04-12 |
| 11302693 | Semiconductor device structure and methods of forming the same | Jia-Chuan You, Kuo-Cheng Chiang, Chih-Hao Wang | 2022-04-12 |
| 11296199 | Semiconductor devices and methods | Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang | 2022-04-05 |
| 11296081 | Integration of silicon channel nanostructures and silicon-germanium channel nanostructures | Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Lun Cheng, Guan-Lin Chen | 2022-04-05 |
| 11289606 | Capacitance reduction for back-side power rail device | Chih-Hao Wang, Kuo-Cheng Chiang, Kuan-Lun Cheng, Wen-Ting Lan | 2022-03-29 |
| 11264327 | Backside power rail structure and methods of forming same | Kuo-Cheng Chiang, Chih-Chao Chou, Wen-Ting Lan, Chih-Hao Wang | 2022-03-01 |
| 11257903 | Method for manufacturing semiconductor structure with hybrid nanostructures | Wen-Ting Lan, Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Ching-Wei Tsai +1 more | 2022-02-22 |
| 11245028 | Isolation structures of semiconductor devices | Jia-Chuan You, Chih-Hao Wang, Kuo-Cheng Chiang, Li-Yang Chuang | 2022-02-08 |
| 11222948 | Semiconductor structure and method of fabricating the semiconductor structure | Guan-Lin Chen, Kuo-Cheng Chiang, Chih-Hao Wang, Jui-Chien Huang | 2022-01-11 |
| 11211381 | Semiconductor device structure and method for forming the same | Kuo-Cheng Chiang, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin | 2021-12-28 |
| 11205714 | Dummy structure at fin cut | Kuo-Cheng Ching, Chih-Hao Wang | 2021-12-21 |
| 11201225 | Structure and formation method of semiconductor device with stressor | Kuo-Cheng Chiang, Guan-Lin Chen, Chih-Hao Wang | 2021-12-14 |
| 11195936 | Semiconductor structure | Kuo-Cheng Ching, Chih-Hao Wang, Ying-Keung Leung | 2021-12-07 |
| 11164866 | Semiconductor structure and method for manufacturing the same | Kuo-Cheng Chiang, Kuan-Lun Cheng, Chih-Hao Wang, Kuan-Ting Pan, Zhi-Chang Lin | 2021-11-02 |
| 11133401 | Fin structures having varied fin heights for semiconductor device | Kuo-Cheng Chiang, Chih-Hao Wang | 2021-09-28 |
| 11121213 | Fin recess last process for FinFET fabrication | Kuo-Cheng Chiang, Guan-Lin Chen | 2021-09-14 |
| 11121036 | Multi-gate device and related methods | Kuo-Cheng Ching, Huan-Chieh Su, Guan-Lin Chen, Chih-Hao Wang | 2021-09-14 |
| 11114529 | Gate-all-around field-effect transistor device | Kuo-Cheng Chiang, Huan-Chieh Su, Kuan-Ting Pan, Chih-Hao Wang | 2021-09-07 |
| 11069793 | Reducing parasitic capacitance for gate-all-around device by forming extra inner spacers | Kuo-Cheng Ching, Chih-Hao Wang, Kuan-Lun Cheng | 2021-07-20 |
| 11038058 | Semiconductor device structure and method for forming the same | Kuo-Cheng Chiang, Ching-Wei Tsai, Kuan-Lun Cheng, Chih-Hao Wang | 2021-06-15 |