Issued Patents All Time
Showing 51–75 of 81 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10664565 | Method and system of expanding set of standard cells which comprise a library | Chi-Lin Liu, Sheng-Hsiung Chen, Jerry Chang Jui Kao, Fong-Yuan Chang, Lee-Chung Lu +1 more | 2020-05-26 |
| 10530345 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu +1 more | 2020-01-07 |
| 10483950 | Level conversion device and method | Yu-Lun Ou, Wei-Chih Hsieh | 2019-11-19 |
| 10380306 | Layout of standard cells for predetermined function in integrated circuits | Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2019-08-13 |
| 10382018 | Flip flop circuit and method of operating the same | Chi-Lin Liu, Lee-Chung Lu, Chang-Yu Wu | 2019-08-13 |
| 10291210 | Level conversion device and method | Yu-Lun Ou, Wei-Chih Hsieh | 2019-05-14 |
| 10289789 | System for designing integrated circuit layout and method of making the integrated circuit layout | Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2019-05-14 |
| 10270432 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu +1 more | 2019-04-23 |
| 10270430 | Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same | Ta-Pen Guo, Chi-Lin Liu, Jerry Chang Jui Kao, Li-Chun Tien, Lee-Chung Lu | 2019-04-23 |
| 10164615 | Level conversion device and method | Yu-Lun Ou, Wei-Chih Hsieh | 2018-12-25 |
| 10003342 | Compressor circuit and compressor circuit layout | Chi-Lin Liu, Lee-Chung Lu, Meng Wang, Henry Huang, Ji-Yung LIN | 2018-06-19 |
| 9887698 | Internal clock gated cell | Chi-Lin Liu, Lee-Chung Lu | 2018-02-06 |
| 9866205 | Level conversion device and method | Yu-Lun Ou, Wei-Chih Hsieh | 2018-01-09 |
| 9853630 | Skew-tolerant flip-flop | Jerry Chang Jui Kao, Chi-Lin Liu, Lee-Chung Lu, Bor-Tyng Lin | 2017-12-26 |
| 9659129 | Standard cell having cell height being non-integral multiple of nominal minimum pitch | Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2017-05-23 |
| 9641161 | Flip-flop with delineated layout for reduced footprint | Chi-Lin Liu, Ting-Wei Chiang, Jerry Chang Jui Kao, Hui-Zhong Zhuang, Lee-Chung Lu +1 more | 2017-05-02 |
| 9584099 | Flip flop circuit | Chi-Lin Liu, Lee-Chung Lu, Chang-Yu Wu | 2017-02-28 |
| 9501600 | Standard cells for predetermined function having different types of layout | Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2016-11-22 |
| 9356583 | Flip-flop circuit | Chi-Lin Liu, Lee-Chung Lu, Chang-Yu Wu | 2016-05-31 |
| 9245887 | Method and layout of an integrated circuit | Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng, Wei-Yu Chen, Hui-Zhong Zhuang +1 more | 2016-01-26 |
| 9203405 | Low-power internal clock gated cell and method | Chi-Lin Liu, Lee-Chung Lu, Meng Wang, Chang-Yu Wu | 2015-12-01 |
| 9158877 | Standard cell metal structure directly over polysilicon structure | Hui-Zhong Zhuang, Ting-Wei Chiang, Chun-Fu Chen, Hsiang-Jen Tseng | 2015-10-13 |
| 9142630 | Device performance enhancement | Chang-Yu Wu, Chih-Chiang Chang, Wei-Chih Hsieh | 2015-09-22 |
| 8698205 | Integrated circuit layout having mixed track standard cell | Jiann-Tyng Tzeng, Chih-Liang Chen, Yi-Feng James Chen, Kam-Tou Sio, Helen Shu-Hui Chang | 2014-04-15 |
| 8667349 | Scan flip-flop circuit having fast setup time | Chih-Chiang Chang, Chang-Yu Wu | 2014-03-04 |