Issued Patents All Time
Showing 51–75 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9768044 | Apparatus and methods for annealing wafers | Yi-Chao Wang, Yu-Chang Lin, Li-Ting Wang, Tai-Chun Huang, Tze-Liang Lee | 2017-09-19 |
| 9647066 | Dummy FinFET structure and method of making same | Chang-Shen Lu, Chih-Tang Peng, Tai-Chun Huang, Hao-Ming Lien, Yi-Hung Lin +2 more | 2017-05-09 |
| 9548366 | Self aligned contact scheme | Tsai-Jung Ho, Kuang-Yuan Hsu | 2017-01-17 |
| 9337059 | Apparatus and methods for annealing wafers | Yi-Chao Wang, Yu-Chang Lin, Li-Ting Wang, Tai-Chun Huang, Tze-Liang Lee | 2016-05-10 |
| 9293581 | FinFET with bottom SiGe layer in source/drain | Ming-Hua Yu, Tze-Liang Lee | 2016-03-22 |
| 9252224 | Self-aligned insulated film for high-k metal gate device | Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo +8 more | 2016-02-02 |
| 9142402 | Uniform shallow trench isolation regions and the method of forming the same | Yu-Ling Liou, Chih-Tang Peng, Hao-Ming Lien, Tze-Liang Lee | 2015-09-22 |
| 8963258 | FinFET with bottom SiGe layer in source/drain | Ming-Hua Yu, Tze-Liang Lee | 2015-02-24 |
| 8822283 | Self-aligned insulated film for high-k metal gate device | Jin-Aun Ng, Maxi Chang, Jen-Sheng Yang, Ta-Wei Lin, Shih-Hao Lo +8 more | 2014-09-02 |
| 8796124 | Doping method in 3D semiconductor device | — | 2014-08-05 |
| 8580653 | Method for fabricating an isolation structure | Tze-Liang Lee, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng +1 more | 2013-11-12 |
| 8574995 | Source/drain doping method in 3D devices | — | 2013-11-05 |
| 8404561 | Method for fabricating an isolation structure | Tze-Liang Lee, Chu-Yun Fu, Chyi Shyuan Chern, Jui-Hei Huang, Chih-Tang Peng +1 more | 2013-03-26 |
| 7915173 | Shallow trench isolation structure having reduced dislocation density | — | 2011-03-29 |
| 7880213 | Bottom electrode of metal-insulator-metal capacitor | Wen-Miao Lo, Lurng-Sheng Lee, Cha-Hsin Lin, Ching-Chiun Wang | 2011-02-01 |
| 7723226 | Interconnects containing bilayer porous low-k dielectrics using different porogen to structure former ratio | Chen-Hua Yu, Yung-Cheng Lu, Chia-Cheng Chou, Keng-Chu Lin, Chung-Chi Ko +2 more | 2010-05-25 |
| 7683438 | Self-aligned double layered silicon-metal nanocrystal memory element, method for fabricating the same, and memory having the memory element | — | 2010-03-23 |
| 7446038 | Interlayer interconnect of three-dimensional memory and method for manufacturing the same | — | 2008-11-04 |
| 7393745 | Method for fabricating self-aligned double layered silicon-metal nanocrystal memory element | — | 2008-07-01 |
| 7157360 | Memory device and method for forming a passivation layer thereon | Hung-Yu Chiu, U-Way Tseng, Wen-Pin Lu, Cheng-Chen Huseh, Fu-Hsiang Hsu | 2007-01-02 |
| 7151042 | Method of improving flash memory performance | Hsuan-Ling Kao | 2006-12-19 |
| 6984553 | Method for forming shallow trench isolation with control of bird beak | — | 2006-01-10 |
| 6939768 | Method of forming self-aligned contacts | — | 2005-09-06 |
| 6908814 | Process for a flash memory with high breakdown resistance between gate and contact | Lin Yang | 2005-06-21 |
| 6867466 | Memory device and method for forming a passivation layer thereon | Hung-Yu Chiu, U-Way Tseng, Wen-Pin Lu, Cheng-Chen Huseh, Fu-Hsiang Hsu | 2005-03-15 |