Issued Patents All Time
Showing 76–97 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6849504 | Method for fabricating flash memory | Ping-Yi Chang | 2005-02-01 |
| 6706611 | Method for patterning a dual damascene with retrograde implantation | — | 2004-03-16 |
| 6664182 | Method of improving the interlayer adhesion property of low-k layers in a dual damascene process | — | 2003-12-16 |
| 6559009 | Method of fabricating a high-coupling ratio flash memory | — | 2003-05-06 |
| 6521548 | Method of forming a spin-on-passivation layer | — | 2003-02-18 |
| 6474257 | High density plasma chemical vapor deposition chamber | — | 2002-11-05 |
| 6472271 | Planarization method of memory unit of flash memory | — | 2002-10-29 |
| 6455440 | Method for preventing polysilicon stringer in memory device | — | 2002-09-24 |
| 6407454 | Inter-metal dielectric layer | Ping-Yi Chang, Chi-Tung Huang | 2002-06-18 |
| 6403424 | Method for forming self-aligned mask read only memory by dual damascene trenches | Chung-Yeh Lee, Henry Chung | 2002-06-11 |
| 6403428 | Method of forming shallow trench isolation | — | 2002-06-11 |
| 6403470 | Method for fabricating a dual damascene structure | — | 2002-06-11 |
| 6391718 | Planarization method for flash memory device | — | 2002-05-21 |
| 6380068 | Method for planarizing a flash memory device | Shu-Li Wu | 2002-04-30 |
| 6372660 | Method for patterning a dual damascene with masked implantation | — | 2002-04-16 |
| 6335259 | Method of forming shallow trench isolation | — | 2002-01-01 |
| 6335274 | Method for forming a high-RI oxide film to reduce fluorine diffusion in HDP FSG process | Shu-Li Wu | 2002-01-01 |
| 6331472 | Method for forming shallow trench isolation | Wan-Yi Liu | 2001-12-18 |
| 6326269 | Method of fabricating self-aligned multilevel mask ROM | C.W. LEE | 2001-12-04 |
| 6319781 | Method of fabricating self-aligned multilevel mask ROM | Chung-Yeh Lee | 2001-11-20 |
| 6303490 | Method for barrier layer in copper manufacture | — | 2001-10-16 |
| 5877074 | Method for improving the electrical property of gate in polycide structure | Chun-Cho Chen | 1999-03-02 |