Issued Patents All Time
Showing 76–100 of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11844209 | Memory cell and method of forming the memory cell | Chia-En Huang | 2023-12-12 |
| 11842781 | Layout structures of memory array and related methods | Yao-Jen Yang, Shao-Yu Chou, Yih Wang | 2023-12-12 |
| 11837300 | Multi-fuse memory cell circuit and method | Chia-En Huang, Shao-Yu Chou, Yih Wang | 2023-12-05 |
| 11837539 | Electrical fuse bit cell in integrated circuit having backside conducting lines | Chien-Ying Chen, Yen-Jen Chen, Yao-Jen Yang, Chia-En Huang | 2023-12-05 |
| 11830827 | Semiconductor memory devices with dielectric fin structures | Chia-En Huang | 2023-11-28 |
| 11823769 | Reducing capacitive loading of memory system based on switches | Chia-En Huang, Yi-Ching Liu, Yih Wang | 2023-11-21 |
| 11817160 | One-time programmable memory bit cell | Yao-Jen Yang, Min-Shin Wu | 2023-11-14 |
| 11803683 | Method of and system for manufacturing semiconductor device | Yao-Jen Yang | 2023-10-31 |
| 11791005 | Memory circuit and method of operating same | Chia-En Huang, Yih Wang | 2023-10-17 |
| 11783107 | Integrated circuit structure | Shao-Yu Chou, Yao-Jen Yang, Chen-Ming Hung | 2023-10-10 |
| 11785766 | E-fuse | Yao-Jen Yang | 2023-10-10 |
| 11763875 | Second word line combined with Y-MUX signal in high voltage memory program | Yoshitaka Yamauchi, Hiroki Noguchi, Perng-Fei Yuh | 2023-09-19 |
| 11756622 | Bank design with differential bulk bias in eFuse array | Chia-En Huang | 2023-09-12 |
| 11756591 | Switches to reduce routing rails of memory system | Chia-En Huang, Yi-Ching Liu, Yih Wang | 2023-09-12 |
| 11756640 | MIM efuse memory devices and fabrication method thereof | Chia-En Huang, Yih Wang | 2023-09-12 |
| 11758715 | System and method for reducing cell area and current leakage in anti-fuse cell array | Chia-En Huang, Shao-Yu Chou, Yih Wang | 2023-09-12 |
| 11723194 | Integrated circuit read only memory (ROM) structure | Geng-Cing Lin, Ze-Sian Lu, Chia-En Huang, Jung-Ping Yang, Yen-Huei Chen | 2023-08-08 |
| 11703650 | Optical fiber protection system | Chien-Fu Tseng | 2023-07-18 |
| 11696437 | Integrated circuit device | Chien-Ying Chen, Chia-En Huang, Yih Wang | 2023-07-04 |
| 11682433 | Multiple stack high voltage circuit for memory | Perng-Fei Yuh, Tung-Cheng Chang, Yih Wang | 2023-06-20 |
| 11664081 | Bit selection for power reduction in stacking structure during memory programming | Yoshitaka Yamauchi, Perng-Fei Yuh | 2023-05-30 |
| 11658114 | Fusible structures and methods of manufacturing same | Shao-Ting Wu, Shao-Yu Chou, Chung-I Huang | 2023-05-23 |
| 11653492 | Memory devices and methods of manufacturing thereof | Chia-En Huang, Yih Wang | 2023-05-16 |
| 11626368 | Semiconductor device having fuse array and method of making the same | Shao-Yu Chou, Po-Hsiang Huang, An-Jiao Fu, Chih-Hao Chen | 2023-04-11 |
| 11621046 | EFuse circuit, method, layout, and structure | Yao-Jen Yang | 2023-04-04 |