Issued Patents All Time
Showing 26–50 of 150 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12243618 | Method of manufacturing semiconductor device | Yao-Jen Yang, Yih Wang, Fu-An Wu | 2025-03-04 |
| 12237264 | Fusible structures | Shao-Ting Wu, Shao-Yu Chou, Chung-I Huang | 2025-02-25 |
| 12230359 | Semiconductor device | Yao-Jen Yang, Yih Wang, Fu-An Wu | 2025-02-18 |
| 12230681 | Semiconductor memory devices with different doping types | Chia-En Huang, Chun Chung Su, Wen-Hsing Hsieh | 2025-02-18 |
| 12224238 | MIM eFuse memory devices and memory array | Chia-En Huang | 2025-02-11 |
| 12218047 | Memory devices and methods of manufacturing thereof | Chia-En Huang, Yi-Hsun Chiu, Yih Wang | 2025-02-04 |
| 12219755 | Anti-fuse device and method | Min-Shin Wu, Shao-Yu Chou, Yao-Jen Yang | 2025-02-04 |
| 12217798 | Bank design with differential bulk bias in eFuse array | Chia-En Huang | 2025-02-04 |
| 12211568 | Multi-fuse memory cell circuit and method | Chia-En Huang, Shao-Yu Chou, Yih Wang | 2025-01-28 |
| 12205648 | Three-dimensional one time programmable memory | Chia-En Huang, Yi-Ching Liu, Yih Wang | 2025-01-21 |
| 12205891 | Methods of manufacturing fusible structures | Shao-Ting Wu, Shao-Yu Chou, Chung-I Huang | 2025-01-21 |
| 12198785 | Semiconductor memory devices with dielectric fin structures | Chia-En Huang | 2025-01-14 |
| 12190927 | Memory device with a bias circuit | Chia-En Huang, Gu-Huan Li | 2025-01-07 |
| 12193204 | Memory devices and methods of manufacturing thereof | Chia-En Huang, Yi-Hsun Chiu, Yih Wang | 2025-01-07 |
| 12193223 | Memory device with improved anti-fuse read current | Chia-En Huang, Yao-Jen Yang, Yih Wang | 2025-01-07 |
| 12176049 | MIM eFuse memory devices and fabrication method thereof | Chia-En Huang, Yih Wang | 2024-12-24 |
| 12165865 | Efuse with fuse walls and method of manufacturing the same | Yao-Jen Yang | 2024-12-10 |
| 12148487 | High-density and high-voltage-tolerable pure core memory cell | Ku-Feng Lin, Perng-Fei Yuh | 2024-11-19 |
| 12112829 | Memory array circuits, memory structures, and methods for fabricating a memory array circuit | Chun-Ying Lee, Chia-En Huang | 2024-10-08 |
| 12094558 | Multiple stack high voltage circuit for memory | Perng-Fei Yuh, Tung-Cheng Chang, Yih Wang | 2024-09-17 |
| 12089402 | Integrated circuit layout and method | Chien-Ying Chen, Chia-En Huang, Yih Wang | 2024-09-10 |
| 12087378 | Bit selection for power reduction in stacking structure during memory programming | Yoshitaka Yamauchi, Perng-Fei Yuh | 2024-09-10 |
| 12080641 | Electrical fuse bit cell in integrated circuit having backside conducting lines | Chien-Ying Chen, Yen-Jen Chen, Yao-Jen Yang, Chia-En Huang | 2024-09-03 |
| 12075614 | MIM memory cell with backside interconnect structures | Chia-En Huang, Yih Wang | 2024-08-27 |
| 12073169 | Anti-fuse array | Shao-Yu Chou, Yao-Jen Yang, Chen-Ming Hung | 2024-08-27 |