Issued Patents All Time
Showing 26–50 of 97 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11923194 | Epitaxial blocking layer for multi-gate devices and fabrication methods thereof | Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang | 2024-03-05 |
| 11908735 | Vias for cobalt-based interconnects and methods of fabrication thereof | Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen | 2024-02-20 |
| 11862708 | Contact plugs and methods forming same | Je-Wei Hsu, Hua Feng Chen, Jyun-Ming Lin, Chen-Huang Peng, Min-Yann Hsieh +1 more | 2024-01-02 |
| 11848373 | Semiconductor devices and methods of manufacture | Wei-Chih Kao, Hsin-Che Chiang, Chun-Sheng Liang | 2023-12-19 |
| 11837602 | Semiconductor device structure having a plurality of threshold voltages and method of forming the same | Yu-San Chien, Hsin-Che Chiang, Chun-Sheng Liang | 2023-12-05 |
| 11804402 | FinFET structure with controlled air gaps | Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen | 2023-10-31 |
| 11804485 | Semiconductor devices and methods of manufacture | Ta-Chun Lin, Jhon Jhy Liaw | 2023-10-31 |
| 11799017 | Semiconductor device structure with uniform threshold voltage distribution and method of forming the same | Wei-Chih Kao, Hsin-Che Chiang, Yu-San Chien, Chun-Sheng Liang | 2023-10-24 |
| 11791217 | Gate structure and method with dielectric gates and gate-cut features | Ta-Chun Lin, Buo-Chin Hsu, Jhon Jhy Liaw, Chih-Yung Lin | 2023-10-17 |
| 11756962 | Semiconductor device | Yu-San Chien, Chun-Sheng Liang, Jhon Jhy Liaw, Hsin-Che Chiang | 2023-09-12 |
| 11749683 | Isolation structure for preventing unintentional merging of epitaxially grown source/drain | Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Mu-Chi Chiang | 2023-09-05 |
| 11749677 | Semiconductor structure and methods of forming the same | Ta-Chun Lin, Jhon Jhy Liaw | 2023-09-05 |
| 11742349 | Semiconductor devices having gate dielectric layers of varying thicknesses and methods of forming the same | Ta-Chun Lin, Jhon Jhy Liaw, Shien-Yang Wu | 2023-08-29 |
| 11728206 | Isolation with multi-step structure | Ta-Chun Lin, Tien-Shao CHUANG, Kuang-Cheng Tai, Chun-Hung Chen, Chih-Hung Hsieh +1 more | 2023-08-15 |
| 11721763 | Semiconductor device and manufacturing method thereof | Wen-Che Tsai, Min-Yann Hsieh, Hua Feng Chen | 2023-08-08 |
| 11688791 | Gate structure and method | Ta-Chun Lin, Jhon Jhy Liaw | 2023-06-27 |
| 11658074 | Structure and method for FinFET device with source/drain modulation | Ta-Chun Lin, Jhon Jhy Liaw | 2023-05-23 |
| 11545573 | Hybrid nanostructure and fin structure device | Ta-Chun Lin, Jhon Jhy Liaw | 2023-01-03 |
| 11532502 | Reducing parasitic capacitance in field-effect transistors | Ta-Chun Lin, Jhon Jhy Liaw | 2022-12-20 |
| 11515199 | Semiconductor structures including standard cells and tap cells | Ta-Chun Lin, Jhon Jhy Liaw | 2022-11-29 |
| 11404309 | Vias for cobalt-based interconnects and methods of fabrication thereof | Yu-Jen Chang, Min-Yann Hsieh, Hua Feng Chen | 2022-08-02 |
| 11374006 | Semiconductor device and method of forming the same | Yu-San Chien, Chun-Sheng Liang, Jhon Jhy Liaw, Hsin-Che Chiang | 2022-06-28 |
| 11362096 | Semiconductor device structure and method for forming the same | Ta-Chun Lin | 2022-06-14 |
| 11349002 | Isolation structure for for isolating epitaxially grown source/drain regions and method of fabrication thereof | Ta-Chun Lin, Kuan-Lin Yeh, Chun-Jun Lin, Mu-Chi Chiang, Jhon Jhy Liaw | 2022-05-31 |
| 11315785 | Epitaxial blocking layer for multi-gate devices and fabrication methods thereof | Hsin-Che Chiang, Wei-Chih Kao, Chun-Sheng Liang | 2022-04-26 |