Issued Patents All Time
Showing 1–25 of 55 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12370661 | Hammer tacker | — | 2025-07-29 |
| 12255105 | Gate-all-around devices having gate dielectric layers of varying thicknesses and method of forming the same | Pei-Hsun Wu, Ming Han, Po-Nien Chen | 2025-03-18 |
| 12243871 | Integrated circuits with capacitors | Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen | 2025-03-04 |
| 12057469 | Semiconductor device and a method of fabricating the same | Yu-Chiun Lin, Po-Nien Chen, Chen-Hua Tsai | 2024-08-06 |
| 11967532 | Gate spacers and methods of forming the same in semiconductor devices | Ta-Chun Lin, Kuo-Hua Pan, Jhon Jhy Liaw | 2024-04-23 |
| 11942375 | Structure and formation method of semiconductor device with fin structures | Hsing-Hui Hsu, Po-Nien Chen, Yi-Hsuan Chung, Bo-Shiuan Shie | 2024-03-26 |
| 11908896 | Integrated circuit structure with non-gated well tap cell | Jiefeng Lin, Jeng-Ya David Yeh | 2024-02-20 |
| 11791217 | Gate structure and method with dielectric gates and gate-cut features | Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw | 2023-10-17 |
| 11728373 | High density capacitor implemented using FinFET | Jiefeng Lin, Hsiao-Lan Yang | 2023-08-15 |
| 11587790 | Integrated circuits with capacitors | Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen | 2023-02-21 |
| 11387321 | Integrated circuit structure with non-gated well tap cell | Jiefeng Lin, Jeng-Ya David Yeh | 2022-07-12 |
| 11210447 | Reconfiguring layout and sizing for transistor components to simultaneously optimize logic devices and non-logic devices | Jiefeng Lin, Dian-Sheg Yu, Hsiao-Lan Yang, Jhon Jhy Liaw | 2021-12-28 |
| 11127639 | Structure and formation method of semiconductor device with fin structures | Zhen Geng, Kitchun Kwong, Taicheng Shieh, Bo-Shiuan Shie, Po-Nien Chen | 2021-09-21 |
| 11094597 | Structure and formation method of semiconductor device with fin structures | Hsing-Hui Hsu, Po-Nien Chen, Yi-Hsuan Chung, Bo-Shiuan Shie | 2021-08-17 |
| 11056396 | Gate-all-around devices having gate dielectric layers of varying thicknesses and method of forming the same | Pei-Hsun Wu, Ming Han, Po-Nien Chen | 2021-07-06 |
| 11037831 | Gate structure and method | Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw | 2021-06-15 |
| 11024703 | Semiconductor device and a method for fabricating the same | Yu-Chiun Lin, Po-Nien Chen, Chen-Hua Tsai | 2021-06-01 |
| 10998237 | Gate structure and method with dielectric gates and gate-cut features | Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw | 2021-05-04 |
| 10879172 | Semiconductor structure | Jiefeng Lin, Hsiao-Lan Yang, Chung-Hui Chen, Hao-Chieh Chan | 2020-12-29 |
| 10861928 | Integrated circuits with capacitors | Hsiao-Han Liu, Hoppy Lee, Chung-Yu Chiang, Po-Nien Chen | 2020-12-08 |
| 10790352 | High density capacitor implemented using FinFET | Jiefeng Lin, Hsiao-Lan Yang | 2020-09-29 |
| 10707315 | Hybrid doping profile | Henry Kwong, Po-Nien Chen, Chen-Hua Tsai | 2020-07-07 |
| 10700160 | Semiconductor device and a method for fabricating the same | Yu-Chiun Lin, Po-Nien Chen, Chen-Hua Tsai | 2020-06-30 |
| 10665673 | Integrated circuit structure with non-gated well tap cell | Jiefeng Lin, Jeng-Ya David Yeh | 2020-05-26 |
| 10629492 | Gate structure having a dielectric gate and methods thereof | Ta-Chun Lin, Buo-Chin Hsu, Kuo-Hua Pan, Jhon Jhy Liaw | 2020-04-21 |