Issued Patents All Time
Showing 1–25 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12402389 | Semiconductor arrangement with airgap and method of forming | Gulbagh Singh, Wang Po-Jen, Tsung-Han Tsai | 2025-08-26 |
| 12302637 | Semiconductor wafer with devices having different top layer thicknesses | Gulbagh Singh, Kuan-Liang Liu, Wang Po-Jen, Hsin-Chi Chen | 2025-05-13 |
| 12230574 | Reducing RC delay in semiconductor devices | Gulbagh Singh, Po-Jen Wang | 2025-02-18 |
| 12211934 | Semiconductor structure and method for manufacturing the same | Gulbagh Singh | 2025-01-28 |
| 12199181 | Semiconductor structure and method for manufacturing the same | Gulbagh Singh | 2025-01-14 |
| 12191196 | Method of manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) having low off-state capacitance | Gulbagh Singh, Tsung-Han Tsai, Shih-Lu HSU | 2025-01-07 |
| 12027581 | Semiconductor device with air-void in spacer | Gulbagh Singh, Hsin-Chi Chen | 2024-07-02 |
| 12009302 | Method of testing wafer | Yen-Hsung Ho, Chia-Yi Tseng, Chih-Hsun Lin, Yung-Lung Hsu | 2024-06-11 |
| 11942547 | Source/drain epitaxial layer profile | Gulbagh Singh, Hsin-Chi Chen | 2024-03-26 |
| 11925017 | Semiconductor device having a wall structure surrounding a stacked gate structure | Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Hung-Che Liao, Chia-Ming Pan +1 more | 2024-03-05 |
| 11887987 | Semiconductor wafer with devices having different top layer thicknesses | Gulbagh Singh, Kuan-Liang Liu, Wang Po-Jen, Hsin-Chi Chen | 2024-01-30 |
| 11855170 | MOSFET device structure with air-gaps in spacer and methods for forming the same | Gulbagh Singh, Po-Jen Wang | 2023-12-26 |
| 11817345 | Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same | Gulbagh Singh, Po-Jen Wang | 2023-11-14 |
| 11804439 | Reducing RC delay in semiconductor devices | Gulbagh Singh, Po-Jen Wang | 2023-10-31 |
| 11594449 | Method of making a semiconductor structure | Chih-Ming Lee, Hung-Che Liao, Wei-Chung Lu | 2023-02-28 |
| 11476157 | Method of manufacturing a metal-oxide-semiconductor field-effect transistor (MOSFET) having low off-state capacitance due to reduction of off-state capacitance of back-end-of-line (BEOL) features of the MOSFET | Gulbagh Singh, Tsung-Han Tsai, Shih-Lu HSU | 2022-10-18 |
| 11462642 | Source/drain epitaxial layer profile | Gulbagh Singh, Hsin-Chi Chen | 2022-10-04 |
| 11430733 | Method of testing wafer | Yen-Hsung Ho, Chia-Yi Tseng, Chih-Hsun Lin, Yung-Lung Hsu | 2022-08-30 |
| 11417749 | Semiconductor arrangement with airgap and method of forming | Gulbagh Singh, Wang Po-Jen, Tsung-Han Tsai | 2022-08-16 |
| 11404537 | Semiconductor device with air-void in spacer | Gulbagh Singh, Hsin-Chi Chen | 2022-08-02 |
| 11398403 | Multiple thickness semiconductor-on-insulator field effect transistors and methods of forming the same | Gulbagh Singh, Po-Jen Wang | 2022-07-26 |
| 11367778 | MOSFET device structure with air-gaps in spacer and methods for forming the same | Gulbagh Singh, Po-Jen Wang | 2022-06-21 |
| 11348944 | Semiconductor wafer with devices having different top layer thicknesses | Gulbagh Singh, Kuan-Liang Liu, Wang Po-Jen, Hsin-Chi Chen | 2022-05-31 |
| 11335638 | Reducing RC delay in semiconductor devices | Gulbagh Singh, Po-Jen Wang | 2022-05-17 |
| 11264456 | Isolation regions for reduced junction leakage | Gulbagh Singh, Hsin-Chi Chen | 2022-03-01 |