Issued Patents All Time
Showing 26–50 of 53 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11211283 | Method for forming a bulk semiconductor substrate configured to exhibit soi behavior | Gulbagh Singh, Hsin-Chi Chen | 2021-12-28 |
| 11183570 | Structures and methods for noise isolation in semiconductor devices | Gulbagh Singh, Tsung-Han Tsai | 2021-11-23 |
| 11171199 | Metal-insulator-metal capacitors with high breakdown voltage | Wei-Ting Chen, Tsung-Han Tsai, Po-Jen Wang, Ying-Hao Chen, Chien-Cheng Huang | 2021-11-09 |
| 11145539 | Shallow trench isolation for integrated circuits | Gulbagh Singh, Hsin-Chi Chen | 2021-10-12 |
| 11121141 | Semiconductor structure and method for forming the same | Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Hung-Che Liao, Hsin-Chi Chen | 2021-09-14 |
| 10964589 | Semiconductor structure | Chih-Ming Lee, Hung-Che Liao, Wei-Chung Lu | 2021-03-30 |
| 10886165 | Method of forming negatively sloped isolation structures | Gulbagh Singh, Tsung-Han Tsai | 2021-01-05 |
| 10818595 | Semiconductor structure, testing and fabricating methods thereof | Yen-Hsung Ho, Chia-Yi Tseng, Chih-Hsun Lin, Yung-Lung Hsu | 2020-10-27 |
| 10790391 | Source/drain epitaxial layer profile | Gulbagh Singh, Hsin-Chi Chen | 2020-09-29 |
| 10672795 | Bulk semiconductor substrate configured to exhibit semiconductor-on-insulator behavior | Gulbagh Singh, Hsin-Chi Chen | 2020-06-02 |
| 10672777 | Method of manufacturing semiconductor device having multi-height structure | Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Chiang-Ming Chuang, Chia-Yi Tseng | 2020-06-02 |
| 10636870 | Isolation regions for reduced junction leakage | Gulbagh Singh, Hsin-Chi Chen | 2020-04-28 |
| 10636695 | Negatively sloped isolation structures | Gulbagh Singh, Tsung-Han Tsai | 2020-04-28 |
| 10546937 | Structures and methods for noise isolation in semiconductor devices | Gulbagh Singh, Tsung-Han Tsai | 2020-01-28 |
| 10535670 | Non-volatile memory having an erase gate formed between two floating gates with two word lines formed on other sides and a method for forming the same | Chien-Hsuan Liu, Chiang-Ming Chuang, Chih-Ming Lee, Hung-Che Liao, Chia-Ming Pan +1 more | 2020-01-14 |
| 10522390 | Shallow trench isolation for integrated circuits | Gulbagh Singh, Hsin-Chi Chen | 2019-12-31 |
| 10283510 | Semiconductor structure and method for forming the same | Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Hung-Che Liao, Hsin-Chi Chen | 2019-05-07 |
| 10283604 | Contact structure for high aspect ratio and method of fabricating the same | Szu-Hsien Lu, Hung-Che Liao, Shih-Lu HSU, Yu-Chu Lin, Jyun-Guan Jhou | 2019-05-07 |
| 10211214 | Semiconductor device having milti-height structure and method of manufacturing the same | Kuan-Wei Su, Yung-Lung Hsu, Chih-Hsun Lin, Chiang-Ming Chuang, Chia-Yi Tseng | 2019-02-19 |
| 10163641 | Memory with a raised dummy feature surrounding a cell region | Chih-Ming Lee, Chiang-Ming Chuang, Yung-Lung Hsu, Hsin-Chi Chen | 2018-12-25 |
| 10037927 | Semiconductor structure, testing and fabricating method thereof | Yen-Hsung Ho, Chia-Yi Tseng, Chih-Hsun Lin, Yung-Lung Hsu | 2018-07-31 |
| 9947759 | Semiconductor device having milti-height structure and method of manufacturing the same | Yu-Shih Lin, Chiang-Ming Chuang, Yung-Lung Hsu | 2018-04-17 |
| 9825046 | Flash memory device having high coupling ratio | Yu-Chu Lin, Hung-Che Liao, Shih-Lu HSU | 2017-11-21 |
| 9768182 | Semiconductor structure and method for forming the same | Chiang-Ming Chuang, Chien-Hsuan Liu, Chih-Ming Lee, Hung-Che Liao, Hsin-Chi Chen | 2017-09-19 |
| 9735049 | Method for fabricating semiconductor structure with passivation sidewall block | Chih-Ming Lee, Hung-Che Liao, Wei-Chung Lu | 2017-08-15 |