Issued Patents All Time
Showing 51–61 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6207482 | Integration method for deep sub-micron dual gate transistor design | Shui-Hung Chen, Jian-Hsing Lee, Chia-Hung Tunga | 2001-03-27 |
| 6207532 | STI process for improving isolation for deep sub-micron application | Chrong-Jung Lin, Shui-Hung Chen | 2001-03-27 |
| 6190954 | Robust latchup-immune CMOS structure | Jian-Hsing Lee, Shui-Hung Chen | 2001-02-20 |
| 6122201 | Clipped sine wave channel erase method to reduce oxide trapping charge generation rate of flash EEPROM | Jian-Hsing Lee, Kuo-Reay Peng, Shui-Hung Chen | 2000-09-19 |
| 6100150 | Process to improve temperature uniformity during RTA by deposition of in situ poly on the wafer backside | Bi-Ling Lin, Huey-Liang Hwang | 2000-08-08 |
| 6097066 | Electro-static discharge protection structure for semiconductor devices | Jian-Hsing Lee, Yi-Hsun Wu | 2000-08-01 |
| 6008974 | Electrostatic discharge protective circuit for reducing an undesired channel turn-on | Jian-Hsing Lee, Yi-Hsun Wu, Jing-Meng Liu | 1999-12-28 |
| 5891792 | ESD device protection structure and process with high tilt angle GE implant | Jian-Hsing Lee | 1999-04-06 |
| 5783850 | Undoped polysilicon gate process for NMOS ESD protection circuits | Siu-han Liau | 1998-07-21 |
| 5723352 | Process to optimize performance and reliability of MOSFET devices | Shion Hann Liaw | 1998-03-03 |
| 5532178 | Gate process for NMOS ESD protection circuits | Shiou-Hann Liaw | 1996-07-02 |