Issued Patents All Time
Showing 26–50 of 61 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6168984 | Reduction of the aspect ratio of deep contact holes for embedded DRAM devices | Ming-Hsiung Chiang, Wen-Chuan Chiang, Cheng-Ming Wu, Tse-Liang Ying | 2001-01-02 |
| 6093616 | Method of manufacture of stacked gate MOS structure for multiple voltage power supply applications | Mong-Song Liang, Jin-Yuan Lee | 2000-07-25 |
| 6071783 | Pseudo silicon on insulator MOSFET device | Mong-Song Liang, Jin-Yuan Lee | 2000-06-06 |
| 6054368 | Method of making an improved field oxide isolation structure for semiconductor integrated circuits having higher field oxide threshold voltages | Cheng-Yeh Shih | 2000-04-25 |
| 6033969 | Method of forming a shallow trench isolation that has rounded and protected corners | R. Y. Lee, J. H. Tsai | 2000-03-07 |
| 6025270 | Planarization process using tailored etchback and CMP | — | 2000-02-15 |
| 6017791 | Multi-layer silicon nitride deposition method for forming low oxidation temperature thermally oxidized silicon nitride/silicon oxide (no) layer | Chen-Jong Wang, Kuo-Hsien Cheng | 2000-01-25 |
| 6015730 | Integration of SAC and salicide processes by combining hard mask and poly definition | Chen-Jong Wang, Jenn Ming Huang | 2000-01-18 |
| 5965927 | Integrated circuit having an opening for a fuse | Jin-Yuan Lee, Hsien-Wei Chin | 1999-10-12 |
| 5943569 | Method for making improved capacitors on dynamic random access memory having increased capacitance, longer refresh times, and improved yields | Cheng-Yeh Shih, Yuan-Chang Huang, Wen Chan Lin | 1999-08-24 |
| 5900658 | Logic and single level polysilicon DRAM devices fabricated on the same semiconductor chip | Jin-Yuan Lee, Mong-Song Liang | 1999-05-04 |
| 5879966 | Method of making an integrated circuit having an opening for a fuse | Jin-Yuan Lee, Hsien-Wei Chin | 1999-03-09 |
| 5866451 | Method of making a semiconductor device having 4t sram and mixed-mode capacitor in logic | Mong-Song Liang, Jin-Yuan Lee | 1999-02-02 |
| 5861673 | Method for forming vias in multi-level integrated circuits, for use with multi-level metallizations | Jin-Yuan Lee | 1999-01-19 |
| 5858830 | Method of making dual isolation regions for logic and embedded memory devices | Mong-Song Liang | 1999-01-12 |
| 5729041 | Protective film for fuse window passivation for semiconductor integrated circuit applications | Jin-Yuan Lee | 1998-03-17 |
| 5726093 | Two-step planer field oxidation method | — | 1998-03-10 |
| 5719079 | Method of making a semiconductor device having high density 4T SRAM in logic with salicide process | Mong-Song Liang, Jin-Yuan Lee | 1998-02-17 |
| 5712201 | Fabrication method for integrating logic and single level polysilicon DRAM devices on the same semiconductor chip | Jin-Yuan Lee, Mong-Song Liang | 1998-01-27 |
| 5670423 | Method for using disposable hard mask for gate critical dimension control | — | 1997-09-23 |
| 5605854 | Integrated Ti-W polycide for deep submicron processing | — | 1997-02-25 |
| 5605853 | Method of making a semiconductor device having 4 transistor SRAM and floating gate memory cells | Mong-Song Liang, Jin-Yuan Lee | 1997-02-25 |
| 5585307 | Forming a semi-recessed metal for better EM and Planarization using a silo mask | — | 1996-12-17 |
| 5578517 | Method of forming a highly transparent silicon rich nitride protective layer for a fuse window | Jin-Yuan Lee | 1996-11-26 |
| 5573980 | Method of forming salicided self-aligned contact for SRAM cells | — | 1996-11-12 |