Issued Patents All Time
Showing 76–100 of 128 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10439794 | Automatic detection of change in PLL locking trend | Tsung-Hsien Tsai | 2019-10-08 |
| 10419005 | Phase-locked-loop architecture | Ruey-Bin Shen, Tsung-Hsien Tsai | 2019-09-17 |
| 10374617 | Injection-locked digital bang-bang phase-locked loop with timing calibration | Ting-Kuei Kuan, CHIN-YANG WU, Ruey-Bin Sheen | 2019-08-06 |
| 10277117 | Device with a voltage multiplier | Yu-Tso Lin, Min-Shueh Yuan, Robert Bogdan Staszewski, Seyednaser Pourmousavian | 2019-04-30 |
| 10222412 | IC degradation management circuit, system and method | Po-Zeng Kang, Wen-Shen Chou, Yung-Chow Peng | 2019-03-05 |
| 10164649 | Hybrid phase lock loop | Tsung-Hsien Tsai, Ruey-Bin Sheen, Cheng-Hsiang Hsieh | 2018-12-25 |
| 10158364 | Realignment strength controller for solving loop conflict of realignment phase lock loop | Tsung-Hsien Tsai, Cheng-Hsiang Hsieh, Ruey-Bin Sheen | 2018-12-18 |
| 10121781 | 3D IC with serial gate MOS device, and method of making the 3D IC | Chao Li, Ruey-Bin Sheen | 2018-11-06 |
| 10090994 | Automatic detection of change in PLL locking trend | Tsung-Hsien Tsai | 2018-10-02 |
| 9943615 | Nanoparticles and method for manufacturing the same | Su-Jung Chen, Chang-An Chen, Chung-Yen Li, Chu-Nian Cheng, Ming-Syuan Lin +1 more | 2018-04-17 |
| 9853807 | Automatic detection of change in PLL locking trend | Tsung-Hsien Tsai | 2017-12-26 |
| 9748933 | Multi-step slew rate control circuits | Chen-Ting Ko, Ruey-Bin Sheen | 2017-08-29 |
| 9707521 | Automated test apparatus for testing risk and integrity of pharmaceutical filtration membranes and method thereof | Ming Li, Shu-Pei Chiu, Te-Wei Lee | 2017-07-18 |
| 9621171 | Frequency scaling method, circuit and associated all-digital phase-locked loop | Tsung-Hsien Tsai | 2017-04-11 |
| 9595474 | 3D IC with serial gate MOS device, and method of making the 3D IC | Chao Li, Ruey-Bin Sheen | 2017-03-14 |
| 9503061 | System and method for calibrating chips in a 3D chip stack architecture | Ying-Yu Hsu, Ruey-Bin Sheen | 2016-11-22 |
| 9455725 | Phase detector and associated phase detecting method | Cheng-Liang Hung, Chun-Cheng Lin, Chao-Hsin Fan Jiang | 2016-09-27 |
| 9450588 | Phase lock loop, voltage controlled oscillator of the phase lock loop, and method of operating the voltage controlled oscillator | Matt Li, Min-Shueh Yuan | 2016-09-20 |
| 9363115 | System and method for aligning data bits | Ying-Yu Hsu, Ruey-Bin Sheen, Shih-Hung Lan | 2016-06-07 |
| 9229050 | BIST circuit for phase measurement | Tsung-Hsien Tsai, Min-Shueh Yuan | 2016-01-05 |
| 9231585 | System and method for calibrating chips in a 3D chip stack architecture | Ying-Yu Hsu, Ruey-Bin Sheen | 2016-01-05 |
| 9165925 | Structures and methods for ring oscillator fabrication | Chao Li, Shyh-An Chi, Ruey-Bin Sheen | 2015-10-20 |
| 9148135 | Real time automatic and background calibration at embedded duty cycle correlation | Matt Li, Tsung-Hsien Tsai, Mao-Hsuan Chou, Min-Shueh Yuan | 2015-09-29 |
| 9099990 | High speed communication interface with an adaptive swing driver to reduce power consumption | Ying-Yu Hsu, Yung-Chow Peng, Min-Shueh Yuan | 2015-08-04 |
| 9035464 | 3D IC with serial gate MOS device, and method of making the 3D IC | Chao Li, Ruey-Bin Sheen | 2015-05-19 |