Issued Patents All Time
Showing 101–121 of 121 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10714592 | Method of manufacturing a semiconductor device and a semiconductor device | Chen-Feng Hsu, Tzu-Chiang Chen, Tung Ying Lee, Wei-Sheng Yun, Yu-Lin Yang | 2020-07-14 |
| 10699956 | Method of manufacturing a semiconductor device and a semiconductor device | Hung-Li Chiang, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang +2 more | 2020-06-30 |
| 10700205 | Method for forming semiconductor structure | Chen-Feng Hsu, Yu-Lin Yang, Jung-Piao Chiu, Tzu-Chiang Chen | 2020-06-30 |
| 10672667 | Semiconductor device and method | Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh | 2020-06-02 |
| 10651314 | Nanowire stack GAA device with inner spacer and methods for producing the same | I-Sheng Chen, Tzu-Chiang Chen, Carlos H. Diaz | 2020-05-12 |
| 10636891 | Method of manufacturing a semiconductor device and a semiconductor device | Yu-Lin Yang, Tung Ying Lee, Shao-Ming Yu, Tzu-Chiang Chen, Chao-Hsien Huang | 2020-04-28 |
| 10629679 | Method of manufacturing a semiconductor device and a semiconductor device | Yu-Lin Yang, Tzu-Chiang Chen, I-Sheng Chen | 2020-04-21 |
| 10522622 | Multi-gate semiconductor device and method for forming the same | I-Sheng Chen, Tzu-Chiang Chen, Shih-Syuan Huang, Hung-Li Chiang | 2019-12-31 |
| 10510827 | Capacitor having multiple graphene structures | Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chun-Chieh Lu, Chi-Feng Huang +3 more | 2019-12-17 |
| 10403550 | Method of manufacturing a semiconductor device and a semiconductor device | Hung-Li Chiang, Chih-Liang Chen, Tzu-Chiang Chen, Ta-Pen Guo, Yu-Lin Yang +2 more | 2019-09-03 |
| 10374059 | Structure and formation method of semiconductor device structure with nanowires | Wei-Sheng Yun, Shao-Ming Yu, Tsung-Lin Lee, Chih Chieh Yeh | 2019-08-06 |
| 10361278 | Method of manufacturing a semiconductor device and a semiconductor device | Yu-Lin Yang, Tung Ying Lee, Shao-Ming Yu, Tzu-Chiang Chen, Chao-Hsien Huang | 2019-07-23 |
| 10355102 | Semiconductor device and method of manufacturing the same | Yu-Lin Yang, Wei-Sheng Yun, Chen-Feng Hsu, Tzu-Chiang Chen | 2019-07-16 |
| 10297508 | Semiconductor device and method | Tzu-Chiang Chen, Chen-Feng Hsu, Yu-Lin Yang, Tung Ying Lee, Chih Chieh Yeh | 2019-05-21 |
| 10283639 | Semiconductor structure and method for forming the same | Chen-Feng Hsu, Yu-Lin Yang, Jung-Piao Chiu, Tzu-Chiang Chen | 2019-05-07 |
| 10134640 | Semiconductor device structure with semiconductor wire | Hung-Li Chiang, I-Sheng Chen, Tzu-Chiang Chen, Chih Chieh Yeh, Yee-Chia Yeo | 2018-11-20 |
| 10062782 | Method of manufacturing a semiconductor device with multilayered channel structure | Chih Chieh Yeh, Cheng-Hsien Wu, Hung-Li Chiang, Jung-Piao Chiu, Tzu-Chiang Chen +3 more | 2018-08-28 |
| 10050104 | Capacitor having a graphene structure, semiconductor device including the capacitor and method of forming the same | Chewn-Pu Jou, Chih-Hsin Ko, Po-Wen Chiu, Chun-Chieh Lu, Chi-Feng Huang +3 more | 2018-08-14 |
| 10038080 | Semiconductor device and manufacturing method thereof | Jung-Piao Chiu, Tsung-Lin Lee, Chih Chieh Yeh | 2018-07-31 |
| 9406518 | (110) surface orientation for reducing fermi-level-pinning between high-K dielectric and group III-V compound semiconductor substrate | Chih-Hsin Ko, Hsingjen Wann | 2016-08-02 |
| 8878302 | Semiconductor device having SiGe substrate, interfacial layer and high K dielectric layer | Ji-Yin Tsai, Cheng-Hsien Wu, Chih-Hsin Ko, Clement Hsingjen Wann | 2014-11-04 |