Issued Patents All Time
Showing 26–31 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6385750 | Method and system for controlling test data volume in deterministic test pattern generation | Rohit Kapur, Thomas W. Williams, John A. Waicukauski | 2002-05-07 |
| 6247165 | System and process of extracting gate-level descriptions from simulation tables for formal verification | Demosthenes Anastasakis | 2001-06-12 |
| 6148436 | System and method for automatic generation of gate-level descriptions from table-based descriptions for electronic design automation | — | 2000-11-14 |
| 5796990 | Hierarchical fault modeling system and method | Mark A. Erle, Matthew C. Graf | 1998-08-18 |
| 5668492 | Integrated circuit clocking technique and circuit therefor | Mark Pedersen | 1997-09-16 |
| 5508641 | Integrated circuit chip and pass gate logic family therefor | David Appenzeller | 1996-04-16 |