Issued Patents All Time
Showing 26–50 of 69 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10388397 | Logic timing and reliability repair for nanowire circuits | Victor Moroz | 2019-08-20 |
| 10381100 | Enhancing memory yield and performance through utilizing nanowire self-heating | Victor Moroz | 2019-08-13 |
| 10372852 | Measurement of Aggressor/Victim capacitive coupling impact on timing | Thu Nguyen, Shih-Yao Christine Sun | 2019-08-06 |
| 10360330 | Evaluation of voltage domains in the presence of leakage and/or dynamic switching | Thu Nguyen | 2019-07-23 |
| 10312229 | Memory cells including vertical nanowire transistors | Victor Moroz, Thu Nguyen | 2019-06-04 |
| 10256223 | Cells having transistors and interconnects including nanowires or 2D material strips | Victor Moroz | 2019-04-09 |
| 10217508 | SRAM and periphery specialized device sensors | Tzong-Kwang Henry Yeh | 2019-02-26 |
| 10037397 | Memory cell including vertical transistors and horizontal nanowire bit lines | Victor Moroz | 2018-07-31 |
| 9953990 | One-time programmable memory using rupturing of gate insulation | Andrew E. Horch, Victor Moroz | 2018-04-24 |
| 9857409 | Negative bias thermal instability stress testing of transistors | Tzong-Kwang Henry Yeh, Shih-Yao Christine Sun, Raymond Leung | 2018-01-02 |
| 9817059 | Evaluation of thermal instability stress testing | Thu Nguyen, Tzong-Kwang Henry Yeh, Shih-Yao Christine Sun, Raymond Leung | 2017-11-14 |
| 9817928 | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits | Victor Moroz | 2017-11-14 |
| 9742406 | Circuit skew compensation trigger system | Thu Nguyen, Raymond Leung | 2017-08-22 |
| 9735227 | 2D material super capacitors | Victor Moroz | 2017-08-15 |
| 9728528 | Method and apparatus for floating or applying voltage to a well of an integrated circuit | Victor Moroz, James David Sproch, Robert B. Lefferts | 2017-08-08 |
| 9691764 | FinFET cell architecture with power traces | Victor Moroz, Deepak D. Sherlekar | 2017-06-27 |
| 9691768 | Nanowire or 2D material strips interconnects in an integrated circuit cell | Victor Moroz | 2017-06-27 |
| 9424951 | Dynamic static random access memory (SRAM) array characterization using an isolated bit-line | Raymond Leung, Tzong-Kwang Henry Yeh, Shih-Yao Christine Sun | 2016-08-23 |
| 9400862 | Cells having transistors and interconnects including nanowires or 2D material strips | Victor Moroz | 2016-07-26 |
| 9378320 | Array with intercell conductors including nanowires or 2D material strips | Victor Moroz | 2016-06-28 |
| 9361418 | Nanowire or 2D material strips interconnects in an integrated circuit cell | Victor Moroz | 2016-06-07 |
| 9287253 | Method and apparatus for floating or applying voltage to a well of an integrated circuit | Victor Moroz, James David Sproch, Robert B. Lefferts | 2016-03-15 |
| 9190346 | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits | Victor Moroz | 2015-11-17 |
| 9184110 | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits | Victor Moroz | 2015-11-10 |
| 9177894 | Latch-up suppression and substrate noise coupling reduction through a substrate back-tie for 3D integrated circuits | Victor Moroz | 2015-11-03 |