| 9891985 |
256-bit parallel parser and checksum circuit with 1-hot state information bus |
Benjamin Findlen |
2018-02-13 |
| 9515946 |
High-speed dequeuing of buffer IDS in frame storing system |
— |
2016-12-06 |
| 9270488 |
Reordering PCP flows as they are assigned to virtual channels |
— |
2016-02-23 |
| 9264256 |
Merging PCP flows as they are assigned to a single virtual channel |
— |
2016-02-16 |
| 9258256 |
Inverse PCP flow remapping for PFC pause frame generation |
— |
2016-02-09 |
| 9208844 |
DDR retiming circuit |
Chunli Cai, Ranjit Loboprabhu |
2015-12-08 |
| 5559459 |
Clock signal generation arrangement including digital noise reduction circuit for reducing noise in a digital clocking signal |
Paul R. Back, Paul R. Carlin |
1996-09-24 |
| 5379381 |
System using separate transfer circuits for performing different transfer operations respectively and scanning I/O devices status upon absence of both operations |
— |
1995-01-03 |
| 5257383 |
Programmable interrupt priority encoder method and apparatus |
— |
1993-10-26 |
| 4974144 |
Digital data processor with fault-tolerant peripheral interface |
William L. Long, Robert F. Wambach, Kurt F. Baty |
1990-11-27 |
| 4974150 |
Fault tolerant digital data processor with improved input/output controller |
William F. Long, Robert F. Wambach, Kurt F. Baty |
1990-11-27 |
| 4939643 |
Fault tolerant digital data processor with improved bus protocol |
William L. Long, Robert F. Wambach, Kurt F. Baty |
1990-07-03 |
| 4931922 |
Method and apparatus for monitoring peripheral device communications |
Kurt F. Baty |
1990-06-05 |
| 4926315 |
Digital data processor with fault tolerant peripheral bus communications |
William L. Long, Robert F. Wambach, Kurt F. Baty, John E. McNamara |
1990-05-15 |