| 10818368 |
Level shifter circuit having two-domain level shifting capability |
Antonino Conte, Leopoldo Maria Marino, Maurizio Francesco Perroni |
2020-10-27 |
$24,833,000 |
| 10249373 |
Circuit and method for reading a memory cell of a non-volatile memory device |
Giovanni Campardo |
2019-04-02 |
$7,176,000 |
| 10186317 |
Phase change memory device and method of operation |
Maurizio Francesco Perroni, Carmelo Paolino |
2019-01-22 |
$5,911,000 |
| 10115462 |
Address decoder for a non-volatile memory array using MOS selection transistors |
Maurizio Francesco Perroni |
2018-10-30 |
$7,428,000 |
| 10002672 |
Memory device with progressive row reading and related reading method |
Giovanni Campardo |
2018-06-19 |
$18,008,000 |
| 9972394 |
Level shifter circuit and associated memory device |
Antonino Conte, Carmelo Paolino, Maurizio Francesco Perroni |
2018-05-15 |
$9,501,000 |
| 9966145 |
Row decoder for a non-volatile memory device, and non-volatile memory device |
Giovanni Campardo |
2018-05-08 |
$21,541,000 |
| 9865356 |
Circuit and method for reading a memory cell of a non-volatile memory device |
Giovanni Campardo |
2018-01-09 |
$7,404,000 |
| 9865346 |
Phase change memory device and method of operation |
Maurizio Francesco Perroni, Carmelo Paolino |
2018-01-09 |
$7,404,000 |
| 9805810 |
Memory device with progressive row reading and related reading method |
Giovanni Campardo |
2017-10-31 |
$12,244,000 |
| 9767907 |
Row decoder for a non-volatile memory device, having reduced area occupation |
Giovanni Campardo |
2017-09-19 |
$9,858,000 |
| 9679655 |
Row decoder for a non-volatile memory device, and non-volatile memory device |
Giovanni Campardo |
2017-06-13 |
$7,514,000 |
| 8982612 |
Row decoder circuit for a phase change non-volatile memory device |
Maurizio Francesco Perroni, Guido Desandre, Giuseppe Castagna |
2015-03-17 |
$1,754,000 |
| 7916526 |
Protection register for a phase-change memory |
Enzo M. Donze, Greg Komoto |
2011-03-29 |
$8,585,000 |
| 7519751 |
Method of generating an enable signal of a standard memory core and relative memory device |
Maurizio Francesco Perroni, Andrea Scavuzzo |
2009-04-14 |
|
| 7408377 |
Driving circuit of an output buffer stage having a high speed and a reduced noise induced on power supply |
Giuseppe Castagna, Salvatore Imbesi, Salvatore Mazzara |
2008-08-05 |
$7,903,000 |
| 7376810 |
Integrated device with multiple reading and/or writing commands |
Maurizio Francesco Perroni, Salvatore Mazzara |
2008-05-20 |
$7,960,000 |
| 7151705 |
Non-volatile memory device architecture, for instance a flash kind, having a serial communication interface |
Maurizio Francesco Perroni, Paolino Schillaci |
2006-12-19 |
$21,176,000 |
| 7139397 |
Hybrid architecture for realizing a random numbers generator |
Marco Messina, Giulio Mangione |
2006-11-21 |
$9,649,000 |
| 6996697 |
Method of writing a group of data bytes in a memory and memory device |
Salvatore Poli, Paolino Schillaci |
2006-02-07 |
$10,934,000 |
| 6990596 |
Memory device outputting read data in a time starting from a rising edge of an external clock that is shorter than that of known devices |
Maurizio Francesco Perroni |
2006-01-24 |
$8,000,000 |
| 6975559 |
Device and method for reading non-volatile memories having at least one pseudo-parallel communication interface |
Maurizio Francesco Perroni, Salvatore Poli |
2005-12-13 |
$10,332,000 |
| 6927991 |
Memory device accessible with different communication protocols |
Maurizio Francesco Perroni, Andrea Scavuzzo |
2005-08-09 |
$5,263,000 |
| 6894914 |
Nonvolatile memory device with parallel and serial functioning mode and selectable communication protocol |
Maurizio Francesco Perroni |
2005-05-17 |
$6,306,000 |
| 6892269 |
Nonvolatile memory device with double serial/parallel communication interface |
Salvatore Poli, Maurizio Francesco Perroni |
2005-05-10 |
$5,656,000 |