Issued Patents All Time
Showing 51–63 of 63 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7851846 | Non-volatile memory cell with buried select gate, and method of making same | Nhan Do, Hieu Van Tran | 2010-12-14 |
| 7829404 | Method of making a semiconductor memory array of floating gate memory cells with program/erase and select gates | Pavel Klinger | 2010-11-09 |
| 7816723 | Semiconductor memory array of floating gate memory cells with program/erase and select gates | Pavel Klinger | 2010-10-19 |
| 7315056 | Semiconductor memory array of floating gate memory cells with program/erase and select gates | Pavel Klinger | 2008-01-01 |
| 7227217 | Nonvolatile memory cell having floating gate, control gate and separate erase gate, an array of such memory cells, and method of manufacturing | Pavel Klinger, Bomy Chen, Hieu Van Tran, Dana Lee, Jack Edward Frayer | 2007-06-05 |
| 7149110 | Seek window verify program system and method for a multilevel non-volatile memory integrated circuit system | Hieu Van Tran, Hung Quoc Nguyen, Isao Nojima | 2006-12-12 |
| 7084453 | Method of forming different oxide thickness for high voltage transistor and memory cell tunnel dielectric | Geeng-Chuan Chern, Dana Lee | 2006-08-01 |
| 6969687 | Method of planarizing a semiconductor die | Gian Sharma | 2005-11-29 |
| 6855980 | Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling | Chih-Hsin Wang | 2005-02-15 |
| 6773974 | Method of forming a semiconductor array of floating gate memory cells and strap regions | Chih-Hsin Wang | 2004-08-10 |
| 6727545 | Semiconductor memory array of floating gate memory cells with low resistance source regions and high source coupling | Chih-Hsin Wang | 2004-04-27 |
| 6703318 | Method of planarizing a semiconductor die | Gian Sharma | 2004-03-09 |
| 6566706 | Semiconductor array of floating gate memory cells and strap regions | Chih-Hsin Wang | 2003-05-20 |