Issued Patents All Time
Showing 51–75 of 184 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11507642 | Configurable input blocks and output blocks and physical layout for analog neural memory in deep learning artificial neural network | Hieu Van Tran, Stephen Trinh, Thuan Vu, Stanley Hong, Vipin Tiwari +1 more | 2022-11-22 |
| 11508442 | Non-volatile memory system using strap cells in source line pull down circuits | Leo Xing, Chunming Wang, Xian Liu, Guangming Lin, Yaohua Zhu | 2022-11-22 |
| 11507816 | Precision tuning for the programming of analog neural memory in a deep learning artificial neural network | Hieu Van Tran, Steven Lemke, Vipin Tiwari, Mark Reiten | 2022-11-22 |
| 11500442 | System for converting neuron current into neuron current-based time pulses in an analog neural memory in a deep learning artificial neural network | Hieu Van Tran, Vipin Tiwari, Mark Reiten | 2022-11-15 |
| 11488970 | Method of forming split gate memory cells with thinner tunnel oxide | Jeng-Wei Yang, Man-Tang Wu, Boolean Fan | 2022-11-01 |
| 11482530 | Precision tuning for the programming of analog neural memory in a deep learning artificial neural network | Hieu Van Tran, Steven Lemke, Vipin Tiwari, Mark Reiten | 2022-10-25 |
| 11449741 | Testing circuitry and methods for analog neural memory in artificial neural network | Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly +3 more | 2022-09-20 |
| 11444091 | Method of making memory cells, high voltage devices and logic devices on a substrate | Jack Sun, Chunming Wang, Xian Liu, Andy Yang, Guo Xiang Song +1 more | 2022-09-13 |
| 11443175 | Compensation for reference transistors and memory cells in analog neuro memory in deep learning artificial neural network | Hieu Van Tran, Vipin Tiwari | 2022-09-13 |
| 11409352 | Power management for an analog neural memory in a deep learning artificial neural network | Hieu Van Tran, Vipin Tiwari, Mark Reiten | 2022-08-09 |
| 11404545 | Method of forming split-gate flash memory cell with spacer defined floating gate and discretely formed polysilicon gates | Chunming Wang, Xian Liu, Leo Xing, Guo Yong Liu, Melvin Diao | 2022-08-02 |
| 11393546 | Testing circuitry and methods for analog neural memory in artificial neural network | Hieu Van Tran, Thuan Vu, Stephen Trinh, Stanley Hong, Anh Ly +3 more | 2022-07-19 |
| 11393535 | Ultra-precise tuning of analog neural memory cells in a deep learning artificial neural network | Steven Lemke, Hieu Van Tran, Yuri Tkachev, Louisa Schneider, Henry A. Om'Mani +2 more | 2022-07-19 |
| 11380698 | Virtual ground non-volatile memory array | Hieu Van Tran, Hung Quoc Nguyen | 2022-07-05 |
| 11373707 | Method and apparatus for configuring array columns and rows for accessing flash memory cells | Hieu Van Tran, Anh Ly, Thuan Vu, Vipin Tiwari | 2022-06-28 |
| 11362218 | Method of forming split gate memory cells with thinned side edge tunnel oxide | Jinho Kim, Elizabeth Cuevas, Yuri Tkachev, Parviz Ghazavi, Bernard Bertello +4 more | 2022-06-14 |
| 11362100 | FinFET split gate non-volatile memory cells with enhanced floating gate to floating gate capacitive coupling | Feng Zhou, Xian Liu, Steven Lemke, Hieu Van Tran | 2022-06-14 |
| 11322507 | Method of making memory cells, high voltage devices and logic devices on a substrate with silicide on conductive blocks | Chunming Wang, Jack Sun, Xian Liu, Leo Xing, Andy Yang +1 more | 2022-05-03 |
| 11316024 | Split-gate non-volatile memory cells with erase gates disposed over word line gates, and method of making same | Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing | 2022-04-26 |
| 11315940 | Method of forming a device with planar split gate non-volatile memory cells, high voltage devices and FinFET logic devices | Chunming Wang, Guo Xiang Song, Leo Xing, Jack Sun, Xian Liu | 2022-04-26 |
| 11315636 | Four gate, split-gate flash memory array with byte erase operation | Hsuan Liang, Man-Tang Wu, Jeng-Wei Yang, Hieu Van Tran, Lihsin Chang | 2022-04-26 |
| 11315635 | Split-gate, 2-bit non-volatile memory cell with erase gate disposed over word line gate, and method of making same | Chunming Wang, Xian Liu, Guo Xiang Song, Leo Xing | 2022-04-26 |
| 11308383 | Deep learning neural network classifier using non-volatile memory array | Farnood Merrikh Bayat, Xinjie Guo, Dmitri Strukov, Hieu Van Tran, Vipin Tiwari +1 more | 2022-04-19 |
| 11270763 | Neural network classifier using array of three-gate non-volatile memory cells | Hieu Van Tran, Steven Lemke, Vipin Tiwari, Mark Reiten | 2022-03-08 |
| 11270771 | Neural network classifier using array of stacked gate non-volatile memory cells | Hieu Van Tran, Steven Lemke, Vipin Tiwari, Mark Reiten | 2022-03-08 |