Issued Patents All Time
Showing 1–9 of 9 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12131786 | Memory cell array with row direction gap between erase gate lines and dummy floating gates | Louisa Schneider, Xian Liu, Steven Lemke, Jinho Kim, Henry A. Om'Mani +2 more | 2024-10-29 |
| 12020762 | Method of determining defective die containing non-volatile memory cells | Yuri Tkachev, Jinho Kim, Cynthia Fung, Gilles Festes, Bernard Bertello +7 more | 2024-06-25 |
| 11362218 | Method of forming split gate memory cells with thinned side edge tunnel oxide | Jinho Kim, Elizabeth Cuevas, Yuri Tkachev, Bernard Bertello, Gilles Festes +4 more | 2022-06-14 |
| 11183506 | Method of making embedded memory device with silicon-on-insulator substrate | Jinho Kim, Xian Liu, Feng Zhou, Steven Lemke, Nhan Do | 2021-11-23 |
| 11018147 | Method of forming split gate memory cells with thinned tunnel oxide | Jinho Kim, Elizabeth Cuevas, Bernard Bertello, Gilles Festes, Catherine Decobert +3 more | 2021-05-25 |
| 10790292 | Method of making embedded memory device with silicon-on-insulator substrate | Jinho Kim, Xian Liu, Feng Zhou, Steven Lemke, Nhan Do | 2020-09-29 |
| 9673208 | Method of forming memory array and logic devices | Jinho Kim, Chien-Sheng Su, Feng Zhou, Xian Liu, Nhan Do +1 more | 2017-06-06 |
| 9564238 | Flash memory system using memory cell as source line pull down circuit | Ning Bai, Hieu Van Tran, Qing Long Rao, Kai Man Yue | 2017-02-07 |
| 8513728 | Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates | Hieu Van Tran, Shiuh-Luen Wang, Nhan Do, Henry A. Om'Mani | 2013-08-20 |