Issued Patents All Time
Showing 1–12 of 12 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12131786 | Memory cell array with row direction gap between erase gate lines and dummy floating gates | Louisa Schneider, Xian Liu, Steven Lemke, Parviz Ghazavi, Jinho Kim +2 more | 2024-10-29 |
| 11393535 | Ultra-precise tuning of analog neural memory cells in a deep learning artificial neural network | Steven Lemke, Hieu Van Tran, Yuri Tkachev, Louisa Schneider, Thuan Vu +2 more | 2022-07-19 |
| 9570581 | Method of forming a self-aligned stack gate structure for use in a non-volatile memory array | Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege +7 more | 2017-02-14 |
| 9330922 | Self-aligned stack gate structure for use in a non-volatile memory array and a method of forming such structure | Willem-Jan Toren, Xian Liu, Gerhard Metzger-Brueckl, Nhan Do, Stephan Wege +7 more | 2016-05-03 |
| 9245638 | Method of operating a split gate flash memory cell with coupling gate | Nhan Do, Elizabeth Cuevas, Yuri Tkachev, Mandana Tadayoni | 2016-01-26 |
| 8711636 | Method of operating a split gate flash memory cell with coupling gate | Nhan Do, Elizabeth Cuevas, Yuri Tkachev, Mandana Tadayoni | 2014-04-29 |
| 8513728 | Array of split gate non-volatile floating gate memory cells having improved strapping of the coupling gates | Parviz Ghazavi, Hieu Van Tran, Shiuh-Luen Wang, Nhan Do | 2013-08-20 |
| 7005911 | Power multiplexer and switch with adjustable well bias for gate breakdown and well protection | — | 2006-02-28 |
| 6842041 | Low-voltage non-degenerative transmitter circuit | Thomas Davies | 2005-01-11 |
| 6717859 | Automatic program- and erase-voltage generation for EEPROM cells | Thomas Davies | 2004-04-06 |
| 6603331 | Low-voltage non-degenerative transmitter circuit | Thomas Davies | 2003-08-05 |
| 6590416 | Supply voltage independent ramp-up circuit | Thomas Davies | 2003-07-08 |