Issued Patents All Time
Showing 1–25 of 37 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8395240 | Bond pad for low K dielectric materials and method for manufacture for semiconductor devices | — | 2013-03-12 |
| 8392863 | Method for circuit layout and rapid thermal annealing method for semiconductor apparatus | Jianhua Ju | 2013-03-05 |
| 8158520 | Method of forming a via structure dual damascene structure for the manufacture of semiconductor integrated circuit devices | — | 2012-04-17 |
| 8106423 | Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors | Hanming Wu, Jiang Zhang, John Chen | 2012-01-31 |
| 8058120 | Integration scheme for strained source/drain CMOS using oxide hard mask | Bei Zhu | 2011-11-15 |
| 8049308 | Bond pad for low K dielectric materials and method for manufacture for semiconductor devices | — | 2011-11-01 |
| 7820500 | Single mask scheme method and structure for integrating PMOS and NMOS transistors using strained silicon | — | 2010-10-26 |
| 7709336 | Metal hard mask method and structure for strained silicon MOS transistors | Hanming Wu, John Chen | 2010-05-04 |
| 7663159 | Seal ring corner design | — | 2010-02-16 |
| 7605470 | Dummy patterns and method of manufacture for mechanical strength of low K dielectric materials in copper interconnect structures for semiconductor devices | — | 2009-10-20 |
| 7591659 | Method and structure for second spacer formation for strained silicon MOS transistors | John Chen, Hanming Wu | 2009-09-22 |
| 7547595 | Integration scheme method and structure for transistors using strained silicon | — | 2009-06-16 |
| 7479699 | Seal ring structures with unlanded via stacks | — | 2009-01-20 |
| 7425488 | Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors | Hanming Wu, Jiang Zhang, John Chen | 2008-09-16 |
| 7335566 | Polysilicon gate doping method and structure for strained silicon MOS transistors | Bei Zhu | 2008-02-26 |
| 7015110 | Method and structure of manufacturing high capacitance metal on insulator capacitors in copper | — | 2006-03-21 |
| 6979526 | Lithography alignment and overlay measurement marks formed by resist mask blocking for MRAMs | — | 2005-12-27 |
| 6972251 | Method for fabricating copper damascene structures in porous dielectric materials | — | 2005-12-06 |
| 6960365 | Vertical MIMCap manufacturing method | — | 2005-11-01 |
| 6815248 | Material combinations for tunnel junction cap layer, tunnel junction hard mask and tunnel junction stack seed layer in MRAM processing | Rainer Leuschner, George Stojakovic | 2004-11-09 |
| 6794262 | MIM capacitor structures and fabrication methods in dual-damascene structures | Keith Kwong Hon Wong | 2004-09-21 |
| 6780775 | Design of lithography alignment and overlay measurement marks on CMP finished damascene surface | — | 2004-08-24 |
| 6750115 | Method for generating alignment marks for manufacturing MIM capacitors | Keith Kwong Hon Wong | 2004-06-15 |
| 6723600 | Method for making a metal-insulator-metal capacitor using plate-through mask techniques | Kwong Hon Wong | 2004-04-20 |
| 6713395 | Single RIE process for MIMcap top and bottom plates | — | 2004-03-30 |