Issued Patents All Time
Showing 1–18 of 18 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11992827 | MSECT-4 molecular sieves with off and ERI topologies, preparation method therefor, and applications thereof | Zhenguo Li, Kaixiang LI, Zhixin Wu, Xiaoning REN, Jianhai Wang +4 more | 2024-05-28 |
| 11699594 | Preparation method for accurate pattern of integrated circuit | — | 2023-07-11 |
| 10552407 | Computing device for data managing and decision making | Chikuan Chen | 2020-02-04 |
| 10515892 | TSV interconnect structure and manufacturing method thereof | Weihai Bu | 2019-12-24 |
| 10128117 | Semiconductor device, related manufacturing method, and related electronic device | Wenbo Wang | 2018-11-13 |
| 9799525 | Semiconductor device, related manufacturing method, and related electronic device | Wenbo Wang | 2017-10-24 |
| 9648985 | Grill device | Zhenshan Huang, Chuntian Qiu | 2017-05-16 |
| 9590031 | Fin-type field effect transistor and manufacturing method thereof | Deyuan Xiao, Mengfeng Cai, Shaofeng Yu, ShiuhWuu Lee | 2017-03-07 |
| 9349588 | Method for fabricating quasi-SOI source/drain field effect transistor device | Ru Huang, Jiewen Fan, Ming Li, Yuancheng Yang, Haoran Xuan +1 more | 2016-05-24 |
| 9024281 | Method for dual energy implantation for ultra-shallow junction formation of MOS devices | Chia-Hao Lee, John Chen | 2015-05-05 |
| 8901675 | CMOS devices and fabrication method | Weihai Bu, Wenbo Wang, Shaofeng Yu | 2014-12-02 |
| 8551831 | Silicon germanium and polysilicon gate structure for strained silicon transistors | Da Wei Gao, Bei Zhu, John Chen, Paolo Bonfanti | 2013-10-08 |
| 8466050 | Method for dual energy implantation for ultra-shallow junction formation of MOS devices | Chia-Hao Lee, John Chen | 2013-06-18 |
| 8106423 | Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors | Jiang Zhang, John Chen, Xian J. Ning | 2012-01-31 |
| 7709336 | Metal hard mask method and structure for strained silicon MOS transistors | Xian J. Ning, John Chen | 2010-05-04 |
| 7591659 | Method and structure for second spacer formation for strained silicon MOS transistors | John Chen, Xian J. Ning | 2009-09-22 |
| 7557000 | Etching method and structure using a hard mask for strained silicon MOS transistors | John Chen, Da Wei Gao, Bei Zhu, Paolo Bonfanti | 2009-07-07 |
| 7425488 | Method and structure using a pure silicon dioxide hardmask for gate patterning for strained silicon MOS transistors | Jiang Zhang, John Chen, Xian J. Ning | 2008-09-16 |