Issued Patents All Time
Showing 51–72 of 72 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6038654 | High performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Yasuaki Hagiwara, Johannes Wang +3 more | 2000-03-14 |
| 5974526 | Superscalar RISC instruction scheduling | Kevin R. Iadonato, Le Trong Nguyen, Johannes Wang | 1999-10-26 |
| 5961629 | High performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Yasuaki Hagiwara, Johannes Wang +3 more | 1999-10-05 |
| 5896542 | System and method for assigning tags to control instruction processing in a superscalar processor | Kevin R. Iadonato, Trevor Deosaran | 1999-04-20 |
| 5892963 | System and method for assigning tags to instructions to control instruction execution | Kevin R. Iadonato, Trevor Deosaran | 1999-04-06 |
| 5838986 | RISC microprocessor architecture implementing multiple typed register sets | Derek J. Lentz, Le Trong Nguyen, Sho Long Chen | 1998-11-17 |
| 5832292 | High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Yasuaki Hagiwara, Johannes Wang +3 more | 1998-11-03 |
| 5826055 | System and method for retiring instructions in a superscalar microprocessor | Johannes Wang, Trevor Deosaran | 1998-10-20 |
| 5809276 | System and method for register renaming | Trevor Deosaran, Kevin R. Iadonato | 1998-09-15 |
| 5737624 | Superscalar risc instruction scheduling | Kevin R. Iadonato, Le Trong Nguyen, Johannes Wang | 1998-04-07 |
| 5689720 | High-performance superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Yasuaki Hagiwara, Johannes Wang +3 more | 1997-11-18 |
| 5682546 | RISC microprocessor architecture implementing multiple typed register sets | Derek J. Lentz, Le Trong Nguyen, Sho Long Chen | 1997-10-28 |
| 5628021 | System and method for assigning tags to control instruction processing in a superscalar processor | Kevin R. Iadonato, Trevor Deosaran | 1997-05-06 |
| 5604912 | System and method for assigning tags to instructions to control instruction execution | Kevin R. Iadonato, Trevor Deosaran | 1997-02-18 |
| 5590295 | System and method for register renaming | Trevor Deosaran, Kevin R. Iadonato | 1996-12-31 |
| 5560032 | High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Yasuaki Hagiwara, Johannes Wang +3 more | 1996-09-24 |
| 5560035 | RISC microprocessor architecture implementing multiple typed register sets | Derek J. Lentz, Le Trong Nguyen, Sho Long Chen | 1996-09-24 |
| 5539911 | High-performance, superscalar-based computer system with out-of-order instruction execution | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Yasuaki Hagiwara, Johannes Wang +3 more | 1996-07-23 |
| 5497499 | Superscalar risc instruction scheduling | Kevin R. Iadonato, Le Trong Nguyen, Johannes Wang | 1996-03-05 |
| 5493687 | RISC microprocessor architecture implementing multiple typed register sets | Derek J. Lentz, Le Trong Nguyen, Sho Long Chen | 1996-02-20 |
| 5481685 | RISC microprocessor architecture implementing fast trap and exception state | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Yasuaki Hagiwara, Johannes Wang +1 more | 1996-01-02 |
| 5448705 | RISC microprocessor architecture implementing fast trap and exception state | Le Trong Nguyen, Derek J. Lentz, Yoshiyuki Miyayama, Yasuaki Hagiwara, Johannes Wang +1 more | 1995-09-05 |