Issued Patents All Time
Showing 126–148 of 148 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6862700 | Memory redundancy with programmable non-volatile control | Theodore Zhu, Gary Kirchner, Richard W. Swanson | 2005-03-01 |
| 6791856 | Methods of increasing write selectivity in an MRAM | Shaoping Li, Theodore Zhu, Anthony Arrott, Harry Hongyue Liu, William Larson | 2004-09-14 |
| 6765820 | Magneto-resistive memory array | Theodore Zhu, Romney R. Katti | 2004-07-20 |
| 6765823 | Magnetic memory cell with shape anisotropy | Theodore Zhu, Anthony Arrott, Joel Drewes | 2004-07-20 |
| 6756240 | Methods of increasing write selectivity in an MRAM | Shaoping Li, Theodore Zhu, Anthony Arrott, Harry Hongyue Liu, William Larson | 2004-06-29 |
| 6735112 | Magneto-resistive memory cell structures with improved selectivity | Theodore Zhu, Anthony Arrott | 2004-05-11 |
| 6717194 | Magneto-resistive bit structure and method of manufacture therefor | Harry Hongyue Liu, William Larson, Lonny Berg, Theodore Zhu, Shaoping Li +2 more | 2004-04-06 |
| 6714441 | Bridge-type magnetic random access memory (MRAM) latch | David E. Fulkerson | 2004-03-30 |
| 6677165 | Magnetoresistive random access memory (MRAM) cell patterning | Theodore Zhu | 2004-01-13 |
| 6671834 | Memory redundancy with programmable non-volatile control | Theodore Zhu, Gary Kirchner, Richard W. Swanson | 2003-12-30 |
| 6590805 | Magneto-resistive memory having sense amplifier with offset control | Michael F. Dries | 2003-07-08 |
| 6556025 | DC/low frequency sub-atto signal level measurement circuit | Arokia Nathan, Tajinder Manku | 2003-04-29 |
| 6522574 | MRAM architectures for increased write selectivity | Shaoping Li, Theodore Zhu, Anthony Arrott, Harry Hongyue Liu, William Larson | 2003-02-18 |
| 6522576 | Magneto-resistive memory array | Theodore Zhu, Romney R. Katti | 2003-02-18 |
| 6493258 | Magneto-resistive memory array | Theodore Zhu, Romney R. Katti | 2002-12-10 |
| 6487111 | Magneto-resistive memory having sense amplifier with offset control | Michael F. Dries | 2002-11-26 |
| 6424561 | MRAM architecture using offset bits for increased write selectivity | Shaoping Li, Theodore Zhu, Anthony Arrott, Harry Hongyue Liu, William Larson | 2002-07-23 |
| 6424564 | MRAM architectures for increased write selectivity | Shaoping Li, Theodore Zhu, Anthony Arrott, Harry Hongyue Liu, William Larson | 2002-07-23 |
| 6396733 | Magneto-resistive memory having sense amplifier with offset control | Michael F. Dries | 2002-05-28 |
| 6363007 | Magneto-resistive memory with shared wordline and sense line | Romney R. Katti | 2002-03-26 |
| 6178111 | Method and apparatus for writing data states to non-volatile storage devices | Jeffrey S. Sather, Theodore Zhu | 2001-01-23 |
| 6175525 | Non-volatile storage latch | David E. Fulkerson, Allen T. Hurst, Jr., Jeffrey S. Sather, Jason Bryce Gadbois | 2001-01-16 |
| 6134138 | Method and apparatus for reading a magnetoresistive memory | Theodore Zhu | 2000-10-17 |