Issued Patents All Time
Showing 1–25 of 31 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 10170495 | Stacked memory device, optical proximity correction (OPC) verifying method, method of designing layout of stacked memory device, and method of manufacturing stacked memory device | Chang-Bum Kim, Sung Hoon Kim, Woo-Joung Kim | 2019-01-01 |
| 10140415 | Method and system for verifying layout of integrated circuit including vertical memory cells | Jae Eun Lee, Sung Hoon Kim, Jae Ick SON | 2018-11-27 |
| 8614908 | Bit line sense amplifier layout array, layout method, and apparatus having the same | Jae-Young Lee, Jong-Hyun Choi | 2013-12-24 |
| 8547766 | Area-efficient data line layouts to suppress the degradation of electrical characteristics | Jong-Hak Won, Choong-Sun Shin, Hak-Soo Yu, Young-Soo An, Jung-Hyeon Kim | 2013-10-01 |
| 8279703 | Sub-word line driver circuit and semiconductor memory device having the same | Jeong Soo Park | 2012-10-02 |
| 8143672 | Semiconductor device including a metal layer having a first pattern and a second pattern which together form a web structure, thereby providing improved electrostatic discharge protection | — | 2012-03-27 |
| 8050125 | Bit line sense amplifier of semiconductor memory device having open bit line structure | Su Yeon KIM | 2011-11-01 |
| 7999297 | Semiconductor device having stacked decoupling capacitors | — | 2011-08-16 |
| 7924604 | Stacked memory cell for use in high-density CMOS SRAM | Uk-Rae Cho | 2011-04-12 |
| 7889532 | Bit line sense amplifier of semiconductor memory device having open bit line structure | Su Yeon KIM | 2011-02-15 |
| 7808852 | Semiconductor memory device and layout method thereof | Wol-Jin Lee | 2010-10-05 |
| 7751273 | Layout structure of sub-world line driver and forming method thereof | — | 2010-07-06 |
| 7639556 | Bit line sense amplifier of semiconductor memory device having open bit line structure | Su Yeon KIM | 2009-12-29 |
| 7564134 | Circuit wiring layout in semiconductor memory device and layout method | Song-Ja Lee | 2009-07-21 |
| 7525173 | Layout structure of MOS transistors on an active region | Su Jin Park, Uk-Rae Cho, Sung Hoon Kim | 2009-04-28 |
| 7436078 | Line layout structure of semiconductor memory device | Kang-Young Kim | 2008-10-14 |
| 7405956 | Line layout structure of semiconductor memory devices | Yun-Jin Jo | 2008-07-29 |
| 7245158 | Circuit wiring layout in semiconductor memory device | Ji-Suk Kwon, Hwa-Jin Kim | 2007-07-17 |
| 7151710 | Semiconductor memory device with data input/output organization in multiples of nine bits | Yong-Hwan Noh, Yun Jin Cho, Chul-Sung Park | 2006-12-19 |
| 7068058 | Semiconductor integrated circuit device with test element group circuit | Chul-Sung Park, Yong-Hwan Noh, Byong-Kwon Lee | 2006-06-27 |
| 7057963 | Dual port SRAM memory | — | 2006-06-06 |
| 6958947 | Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits | Chul-Sung Park, Seung Min Lee, Yong-Hwan Noh | 2005-10-25 |
| 6949960 | Semiconductor integrated circuit comprising functional modes | Chul-Sung Park, Hong Kyun Kim, Yong-Hwan Noh | 2005-09-27 |
| 6909661 | Semiconductor memory device with data input/output organization in multiples of nine bits | Yong-Hwan Noh, Yun Jin Cho, Chul-Sung Park | 2005-06-21 |
| 6822330 | Semiconductor integrated circuit device with test element group circuit | Chul-Sung Park, Yong-Hwan Noh, Byong-Kwon Lee | 2004-11-23 |