Issued Patents All Time
Showing 1–16 of 16 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 12417142 | Method of operating memory for having high reliability and memory of implementing the same | — | 2025-09-16 |
| 12332746 | Method of restoring data and memory of performing the same | Seung Min Lee, Dong-Min Kim, Hyo Chang Kim | 2025-06-17 |
| 8030958 | System for providing a reference voltage to a semiconductor integrated circuit | — | 2011-10-04 |
| 7902871 | Level shifter and semiconductor device having off-chip driver | Chul-Sung Park | 2011-03-08 |
| 7801052 | Apparatus for measuring transmission delay | — | 2010-09-21 |
| 7151710 | Semiconductor memory device with data input/output organization in multiples of nine bits | Hyang-Ja Yang, Yun Jin Cho, Chul-Sung Park | 2006-12-19 |
| 7068058 | Semiconductor integrated circuit device with test element group circuit | Chul-Sung Park, Byong-Kwon Lee, Hyang-Ja Yang | 2006-06-27 |
| 6958947 | Semiconductor memory device with internal voltage generators for testing a memory array and peripheral circuits | Chul-Sung Park, Hyang-Ja Yang, Seung Min Lee | 2005-10-25 |
| 6949960 | Semiconductor integrated circuit comprising functional modes | Chul-Sung Park, Hyang-Ja Yang, Hong Kyun Kim | 2005-09-27 |
| 6909661 | Semiconductor memory device with data input/output organization in multiples of nine bits | Hyang-Ja Yang, Yun Jin Cho, Chul-Sung Park | 2005-06-21 |
| 6822330 | Semiconductor integrated circuit device with test element group circuit | Chul-Sung Park, Byong-Kwon Lee, Hyang-Ja Yang | 2004-11-23 |
| 6674686 | Method and apparatus for read operation and write operation in semiconductor memory device | Young-Ho Suh | 2004-01-06 |
| 6549994 | Semiconductor memory device capable of performing a write operation 1 or 2 cycles after receiving a write command without a dead cycle | — | 2003-04-15 |
| 6483770 | Synchronous semiconductor memory device and method for operating same | Kyo-Min Sohn | 2002-11-19 |
| 6456551 | Semiconductor memory device having prefetch operation mode and data transfer method for reducing the number of main data lines | Kyo-Min Sohn | 2002-09-24 |
| 6269050 | Internal clock generating circuit of synchronous type semiconductor memory device and method thereof | Kook-Hwan Kwon | 2001-07-31 |