Issued Patents All Time
Showing 1–25 of 49 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11437320 | Semiconductor devices | Suk Youn, Chan-Ho Lee, Woo-Jin Jung, Kyu Won Choi | 2022-09-06 |
| 9537470 | Semiconductor device and method for operating the same | Chung-Hee Kim, Min Su Kim, Ji-Kyum Kim, Emil Kagramanyan, Dae Seong Lee +1 more | 2017-01-03 |
| 9318607 | Semiconductor device and method of fabricating the same | Jae-Woo Seo, Gun-Ok Jung, Min Su Kim, Sang-shin Han, Ju-Hyun Kang | 2016-04-19 |
| 9130550 | Semiconductor device and method for operating the same | Chung-Hee Kim, Min Su Kim, Ji-Kyum Kim, Emil Kagramanyan, Dae Seong Lee +1 more | 2015-09-08 |
| 8578227 | Delay test device and system-on-chip having the same | Young-Jae Son, Yong-Jin Yoon | 2013-11-05 |
| 8531208 | Flip-flop and semiconductor device including the same | Gun-Ok Jung, Min Su Kim, Dae-young Moon, Hyoung-Wook Lee | 2013-09-10 |
| 7924604 | Stacked memory cell for use in high-density CMOS SRAM | Hyang-Ja Yang | 2011-04-12 |
| 7825710 | Delay-locked loop circuits and method for generating transmission core clock signals | Nam-Seog Kim | 2010-11-02 |
| 7697314 | Data line layout and line driving method in semiconductor memory device | Nam-Seog Kim, Hak-Soo Yu | 2010-04-13 |
| 7656723 | Semiconductor memory device with hierarchical bit line structure | Nam-Seog Kim, Jong-Cheol Lee, Hak-Soo Yu | 2010-02-02 |
| 7616512 | Semiconductor memory device with hierarchical bit line structure | Nam-Seog Kim, Jong-Cheol Lee, Hak-Soo Yu | 2009-11-10 |
| 7551013 | Phase interpolation circuit and method of generating phase interpolation signal | Nam-Seog Kim | 2009-06-23 |
| 7548086 | Impedance control circuit in semiconductor device and impedance control method | Tae H. Kim, Ji-Suk Kwon | 2009-06-16 |
| 7525173 | Layout structure of MOS transistors on an active region | Hyang-Ja Yang, Su Jin Park, Sung Hoon Kim | 2009-04-28 |
| 7489570 | Semiconductor memory device with hierarchical bit line structure | Nam-Seog Kim, Jong-Cheol Lee, Hak-Soo Yu | 2009-02-10 |
| 7471109 | Output impedance circuit and output buffer circuit including the same | Tae H. Kim | 2008-12-30 |
| 7454672 | Semiconductor memory device testable with a single data rate and/or dual data rate pattern in a merged data input/output pin test mode | Jong-Cheol Lee, Su-Chul Kim | 2008-11-18 |
| 7400177 | Amplifier circuit having constant output swing range and stable delay time | Nam-Seog Kim, Yong-Jin Yoon | 2008-07-15 |
| 7385414 | Impedance controllable ouput drive circuit in semiconductor device and impedance control method therefor | Tae H. Kim, Ji-Suk Kwon | 2008-06-10 |
| 7307441 | Integrated circuit chips and wafers including on-chip test element group circuits, and methods of fabricating and testing same | Kwon Sohn, Su-Chul Kim | 2007-12-11 |
| 7295489 | Method and circuit for writing double data rate (DDR) sampled data in a memory device | Yong-Jin Yoon, Jong-Cheol Lee | 2007-11-13 |
| 7274580 | Content addressable memory device | Tae Gyoung Kang | 2007-09-25 |
| 7187214 | Amplifier circuit having constant output swing range and stable delay time | Nam-Seog Kim, Yong-Jin Yoon | 2007-03-06 |
| 7170318 | Impedance controller and impedance control method | Tae H. Kim, Nam-Seog Kim | 2007-01-30 |
| 7154312 | Apparatus for generating internal clock signal | Nam-Seog Kim, Yong-Jin Yoon | 2006-12-26 |