Issued Patents All Time
Showing 26–32 of 32 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11650793 | Processing element, neural processing device including same, and method for calculating thereof | — | 2023-05-16 |
| 11347517 | Reduced precision based programmable and SIMD dataflow architecture | Kailash Gopalakrishnan, Sunil K. Shukla, Jungwook Choi, Silvia M. Mueller, Bruce M. Fleischer +2 more | 2022-05-31 |
| 11216281 | Facilitating data processing using SIMD reduction operations across SIMD lanes | Bruce M. Fleischer, Kailash Gopalakrishnan, Sunil K. Shukla, Silvia M. Mueller | 2022-01-04 |
| 11138010 | Loop management in multi-processor dataflow architecture | Chia-Yu Chen, Jungwook Choi, Brian W. Curran, Bruce M. Fleischer, Kailash Gopalakrishnan +2 more | 2021-10-05 |
| 10838868 | Programmable data delivery by load and store agents on a processing chip interfacing with on-chip memory components and directing data to external memory components | Chia-Yu Chen, Jungwook Choi, Brian W. Curran, Bruce M. Fleischer, Kailash Gopalakrishan +3 more | 2020-11-17 |
| 10528356 | Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits | Chia-Yu Chen, Kailash Gopalakrishnan, Lee McCall Saltzman, Sunil K. Shukla, Vijayalakshmi Srinivasan | 2020-01-07 |
| 10120685 | Tightly coupled processor arrays using coarse grained reconfigurable architecture with iteration level commits | Chia-Yu Chen, Kailash Gopalakrishnan, Sunil K. Shukla, Vijayalakshmi Srinivasan | 2018-11-06 |