Issued Patents All Time
Showing 76–100 of 110 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 6950956 | Integrated circuit with timing adjustment mechanism and method | Jared L. Zerbe, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu +5 more | 2005-09-27 |
| 6854030 | Integrated circuit device having a capacitive coupling element | Donald V. Perino, Haw-Jyh Liaw, Alfredo Moncayo, Richard M. Barth, Bruno W. Garlepp | 2005-02-08 |
| 6836521 | Apparatus and method for generating a distributed clock signal using gear ratio techniques | Frederick A. Ware, Ely Tsern, Srinivas Nimmagadda | 2004-12-28 |
| 6687780 | Expandable slave device system | Bruno W. Garlepp, Richard M. Barth, Ely Tsern, Craig E. Hampel, Jeffrey D. Mitchell +4 more | 2004-02-03 |
| 6684263 | Apparatus and method for topography dependent signaling | Mark A. Horowitz, Richard M. Barth, Craig E. Hampel, Alfredo Moncayo, Jared L. Zerbe | 2004-01-27 |
| 6642746 | Phase detector with minimized phase detection error | Thomas H. Lee, Tsyr-Chyang Ho | 2003-11-04 |
| 6643752 | Transceiver with latency alignment circuitry | Mark G. Johnson, Chanh Tran, John B. Dillon | 2003-11-04 |
| 6643787 | Bus system optimization | Jared L. Zerbe, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz, Leung Yu +5 more | 2003-11-04 |
| 6553452 | Synchronous memory device having a temperature register | Bruno W. Garlepp, Pak Shing Chau, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos +3 more | 2003-04-22 |
| 6539072 | Delay locked loop circuitry for clock delay adjustment | Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson, Benedict Lau +7 more | 2003-03-25 |
| 6530062 | Active impedance compensation | Haw-Jyh Liaw, Donald V. Perino, Pak Shing Chau | 2003-03-04 |
| 6516365 | Apparatus and method for topography dependent signaling | Mark A. Horowitz, Richard M. Barth, Craig E. Hampel, Alfredo Moncayo, Jared L. Zerbe | 2003-02-04 |
| 6513103 | Method and apparatus for adjusting the performance of a synchronous memory system | Bruno W. Garlepp, Pak Shing Chau, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos +3 more | 2003-01-28 |
| 6496889 | Chip-to-chip communication system using an ac-coupled bus and devices employed in same | Donald V. Perino, Haw-Jyh Liaw, Alfredo Moncayo, Richard M. Barth, Bruno W. Garlepp | 2002-12-17 |
| 6480035 | Phase detector with minimized phase detection error | Thomas H. Lee, Tsyr-Chyang Ho | 2002-11-12 |
| 6448813 | Output driver circuit with well-controlled output impedance | Bruno W. Garlepp, Jared L. Zerbe | 2002-09-10 |
| 6426984 | Apparatus and method for reducing clock signal phase skew in a master-slave system with multiple latent clock cycles | Donald V. Perino, Haw-Jyh Liaw | 2002-07-30 |
| 6396887 | Apparatus and method for generating a distributed clock signal using gear ratio techniques | Frederick A. Ware, Ely Tsern, Srinivas Nimmagadda | 2002-05-28 |
| 6369626 | Low pass filter for a delay locked loop circuit | Andy Peng-Pui Chan, Thomas H. Lee, Wayne S. Richardson, Jared L. Zerbe, Chaofeng Huang +2 more | 2002-04-09 |
| 6340900 | Phase detector with minimized phase detection error | Thomas H. Lee, Tsyr-Chyang Ho | 2002-01-22 |
| RE37452 | At frequency phase shifting circuit for use in a quadrature clock generator | Pak Shing Chau | 2001-11-20 |
| 6321282 | Apparatus and method for topography dependent signaling | Mark A. Horowitz, Richard M. Barth, Craig E. Hampel, Alfredo Moncayo, Jared L. Zerbe | 2001-11-20 |
| 6198307 | Output driver circuit with well-controlled output impedance | Bruno W. Garlepp, Jared L. Zerbe | 2001-03-06 |
| 6133773 | Variable delay element | Bruno W. Garlepp, Pak Shing Chau, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos +3 more | 2000-10-17 |
| 6125157 | Delay-locked loop circuitry for clock delay adjustment | Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson, Benedict Lau +6 more | 2000-09-26 |