Issued Patents All Time
Showing 51–75 of 96 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 7809088 | Multiphase receiver with equalization | Jared L. Zerbe, Pak Shing Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos +2 more | 2010-10-05 |
| 7715501 | Partial response receiver | Vladimir Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew Ho +2 more | 2010-05-11 |
| 7715509 | Partial response receiver | Vladimir Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew Ho +2 more | 2010-05-11 |
| 7706480 | Partial response receiver | Vladimir Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew Ho +2 more | 2010-04-27 |
| 7626442 | Low latency multi-level communication interface | Jared L. Zerbe, Pak Shing Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos +2 more | 2009-12-01 |
| 7627029 | Margin test methods and circuits | Andrew Ho, Vladimir Stojanovic, Fred F. Chen | 2009-12-01 |
| 7590175 | DFE margin test methods and circuits that decouple sample and feedback timing | Brian S. Leibowitz | 2009-09-15 |
| 7536494 | Expandable slave device system with buffered subsystems | Richard M. Barth, Kevin S. Donnelly, Ely Tsern, Craig E. Hampel, Jeffrey D. Mitchell +4 more | 2009-05-19 |
| 7535933 | Calibrated data communication system and method | Jared L. Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz +5 more | 2009-05-19 |
| 7433397 | Partial response receiver with clock data recovery | Jared L. Zerbe, Metha Jeeradit, Vladimir Stojanovic | 2008-10-07 |
| 7397848 | Partial response receiver | Vladimir Stojanovic, Mark A. Horowitz, Jared L. Zerbe, Anthony Bessios, Andrew Ho +2 more | 2008-07-08 |
| 7337294 | Method and apparatus for adjusting the performance of a synchronous memory system | Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos +3 more | 2008-02-26 |
| 7336749 | Statistical margin test methods and circuits | — | 2008-02-26 |
| 7308044 | Technique for receiving differential multi-PAM signals | Jared L. Zerbe, Grace Tsang, Mark A. Horowitz, Carl W. Werner | 2007-12-11 |
| 7308065 | Delay locked loop circuitry for clock delay adjustment | Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson +7 more | 2007-12-11 |
| 7262725 | Digital expander for generating multiple analog control signals particularly useful for controlling an oscillator | Yunteng Huang, David R. Welland | 2007-08-28 |
| 7254797 | Input/output cells with localized clock routing | — | 2007-08-07 |
| 7233164 | Offset cancellation in a multi-level signaling system | Vladimir Stojanovic, Andrew Ho, Fred F. Chen | 2007-06-19 |
| 7222209 | Expandable slave device system | Richard M. Barth, Kevin S. Donnelly, Ely Tsern, Craig E. Hampel, Jeffrey D. Mitchell +4 more | 2007-05-22 |
| 7193467 | Differential amplifiers and methods of using same | Andrew Ho | 2007-03-20 |
| 7149856 | Method and apparatus for adjusting the performance of a synchronous memory system | Pak Shing Chau, Kevin S. Donnelly, Clemenz Portmann, Donald C. Stark, Stefanos Sidiropoulos +3 more | 2006-12-12 |
| 7148753 | Method and apparatus for generating a clock signal in holdover mode | Gerard Pepenella | 2006-12-12 |
| 7130944 | Chip-to-chip communication system using an ac-coupled bus and devices employed in same | Donald V. Perino, Haw-Jyh Liaw, Alfredo Moncayo, Kevin S. Donnelly, Richard M. Barth | 2006-10-31 |
| 7126510 | Circuit calibration system and method | Elad Alon, Vladimir Stojanovic, Andrew Ho, Fred F. Chen | 2006-10-24 |
| 7124221 | Low latency multi-level communication interface | Jared L. Zerbe, Pak Shing Chau, Kevin S. Donnelly, Mark A. Horowitz, Stefanos Sidiropoulos +2 more | 2006-10-17 |