Issued Patents All Time
Showing 26–50 of 100 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9164933 | Memory system with calibrated data communication | Jared L. Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz +5 more | 2015-10-20 |
| 9165617 | Memory controller with staggered request signal output | Ian Shaeffer, Bret G. Stott | 2015-10-20 |
| 9105325 | Memory controller for strobe-based memory systems | Jade M. Kizer, Sivakumar Doraiswamy | 2015-08-11 |
| 8948212 | Memory controller with circuitry to set memory device-specific reference voltages | Jared L. Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz +5 more | 2015-02-03 |
| 8743635 | Memory controller for strobe-based memory systems | Jade M. Kizer, Sivakumar Doraiswamy | 2014-06-03 |
| 8638637 | Memory controller with staggered request signal output | Ian Shaeffer, Bret G. Stott | 2014-01-28 |
| 8630317 | Memory system with calibrated data communication | Jared L. Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz +5 more | 2014-01-14 |
| 8378699 | Self-test method for interface circuit | Bret G. Stott, Philip Yeung, John Brooks, Chanh Tran, Eugene C. Ho | 2013-02-19 |
| 8339878 | Integrated circuit with staggered signal output | Ian Shaeffer, Bret G. Stott | 2012-12-25 |
| 8278968 | Calibration methods and circuits to calibrate drive current and termination impedance | Huy M. Nguyen, Vijay Gadde | 2012-10-02 |
| 8170067 | Memory system with calibrated data communication | Jared L. Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz +5 more | 2012-05-01 |
| 8151133 | Method for calibrating read operations in a memory system | Jade M. Kizer, Sivakumar Doraiswamy | 2012-04-03 |
| 8089824 | Memory controller with staggered request signal output | Ian Shaeffer, Bret G. Stott | 2012-01-03 |
| 7932755 | Phase synchronization for wide area integrated circuits | Huy M. Nguyen, Leung Yu, Jade M. Kizer | 2011-04-26 |
| 7928757 | Calibration methods and circuits to calibrate drive current and termination impedance | Huy M. Nguyen, Vijay Gadde | 2011-04-19 |
| 7741868 | Calibration methods and circuits to calibrate drive current and termination impedance | Huy M. Nguyen, Vijay Gadde | 2010-06-22 |
| 7564258 | Calibration methods and circuits to calibrate drive current and termination impedance | Huy M. Nguyen, Vijay Gadde | 2009-07-21 |
| 7558150 | Memory controller with staggered request signal output | Ian Shaeffer, Bret G. Stott | 2009-07-07 |
| 7543172 | Strobe masking in a signaling system having multiple clock domains | Jade M. Kizer, Sivakumar Doraiswamy | 2009-06-02 |
| 7535933 | Calibrated data communication system and method | Jared L. Zerbe, Kevin S. Donnelly, Stefanos Sidiropoulos, Donald C. Stark, Mark A. Horowitz +5 more | 2009-05-19 |
| 7535242 | Interface test circuit | Bret G. Stott, Philip Yeung, John Brooks, Chanh Tran, Eugene C. Ho | 2009-05-19 |
| 7525338 | Calibration methods and circuits for optimized on-die termination | Huy M. Nguyen, Vijay Gadde | 2009-04-28 |
| 7321524 | Memory controller with staggered request signal output | Ian Shaeffer, Bret G. Stott | 2008-01-22 |
| 7307461 | System and method for adaptive duty cycle optimization | Huy M. Nguyen, Roxanne Vu, Leung Yu | 2007-12-11 |
| 7308065 | Delay locked loop circuitry for clock delay adjustment | Kevin S. Donnelly, Pak Shing Chau, Mark A. Horowitz, Thomas H. Lee, Mark G. Johnson +7 more | 2007-12-11 |