Issued Patents All Time
Showing 251–275 of 322 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8681536 | Magnetic tunnel junction (MTJ) on planarized electrode | Seung H. Kang, Wei-Chuan Chen, Kangho Lee, Xiaochun Zhu, Wah Nam Hsu | 2014-03-25 |
| 8680504 | Diamond type quad-resistor cells of PRAM | — | 2014-03-25 |
| 8674465 | MRAM device and integration techniques compatible with logic integration | Xiaochun Zhu, Seung H. Kang | 2014-03-18 |
| 8642990 | Diamond type quad-resistor cells of PRAM | — | 2014-02-04 |
| 8644063 | Fabrication and integration of devices with top and bottom electrodes including magnetic tunnel junctions | Seung H. Kang | 2014-02-04 |
| 8634231 | Magnetic tunnel junction structure | — | 2014-01-21 |
| 8614912 | Magnetic random access memory (MRAM)layout with uniform pattern | Kangho Lee, Taehyun Kim, Jung Pill Kim, Seung H. Kang | 2013-12-24 |
| 8587982 | Non-volatile memory array configurable for high performance and high density | Jung Pill Kim, Hari M. Rao, Xiaochun Zhu, Seung H. Kang | 2013-11-19 |
| 8582354 | Method and apparatus for testing a resistive memory element | Wah Nam Hsu, Jung Pill Kim, Taehyun Kim, Seung H. Kang | 2013-11-12 |
| 8580583 | Magnetic tunnel junction device and fabrication | Kangho Lee, Xiaochun Zhu, Seung H. Kang | 2013-11-12 |
| 8576617 | Circuit and method for generating a reference level for a magnetic random access memory element | Xiaochun Zhu, Wenqing Wu, Jung Pill Kim, Seung H. Kang | 2013-11-05 |
| 8564080 | Magnetic storage element utilizing improved pinned layer stack | Wei-Chuan Chen, Seung H. Kang, Xiaochun Zhu | 2013-10-22 |
| 8564079 | STT MRAM magnetic tunnel junction architecture and integration | Seung H. Kang, Shiqun Gu, Kangho Lee, Xiaochun Zhu | 2013-10-22 |
| 8557610 | Methods of integrated shielding into MTJ device for MRAM | Wei-Chuan Chen, Seung H. Kang | 2013-10-15 |
| 8558331 | Magnetic tunnel junction device | Xiaochun Zhu, Seung H. Kang, Kangho Lee | 2013-10-15 |
| 8547736 | Generating a non-reversible state at a bitcell having a first magnetic tunnel junction and a second magnetic tunnel junction | Hari M. Rao, Jung Pill Kim, Seung H. Kang, Xiaochun Zhu, Tae Hyun Kim +8 more | 2013-10-01 |
| 8543964 | Constraint optimization of sub-net level routing in asic design | Liang Ge, Jia Tang, Xiao Feng Tang, Chen Xu | 2013-09-24 |
| 8536669 | Magnetic element with storage layer materials | Xiaochun Zhu, Seung H. Kang | 2013-09-17 |
| 8492858 | Magnetic tunnel junction device and fabrication | Seung H. Kang | 2013-07-23 |
| 8483997 | Predictive modeling of contact and via modules for advanced on-chip interconnect technology | Wei Zhao, David Bang, Yu Cao, Seung H. Kang, Matthew Michael Nowak | 2013-07-09 |
| 8458641 | Method, system, and design structure for making voltage environment consistent for reused sub modules in chip design | Xiao Feng Tang, Chen Xu, Jia Tang | 2013-06-04 |
| 8455965 | Fabrication and integration of devices with top and bottom electrodes including magnetic tunnel junctions | Seung H. Kang | 2013-06-04 |
| 8455267 | Magnetic tunnel junction device and fabrication | Seung H. Kang, Xiaochun Zhu | 2013-06-04 |
| 8446753 | Reference cell write operations at a memory | Jung Pill Kim, Hari M. Rao | 2013-05-21 |
| 8441850 | Magnetic random access memory (MRAM) layout with uniform pattern | Kangho Lee, Tae Hyun Kim, Jung Pill Kim, Seung H. Kang | 2013-05-14 |