Issued Patents All Time
Showing 26–47 of 47 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 8145883 | Preloading instructions from an instruction set other than a currently executing instruction set | Thomas Andrew Sartorius, Rodney Wayne Smith | 2012-03-27 |
| 8082428 | Methods and system for resolving simultaneous predicted branch instructions | Rodney Wayne Smith, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2011-12-20 |
| 7984279 | System and method for using a working global history register | James Norris Dieffenderfer, Thomas Andrew Sartorius, Rodney Wayne Smith | 2011-07-19 |
| 7971044 | Link stack repair of erroneous speculative update | James Norris Dieffenderfer, Rodney Wayne Smith | 2011-06-28 |
| 7962725 | Pre-decoding variable length instructions | Rodney Wayne Smith | 2011-06-14 |
| 7917731 | Method and apparatus for prefetching non-sequential instruction addresses | Thomas Andrew Sartorius, Rodney Wayne Smith | 2011-03-29 |
| 7827392 | Sliding-window, block-based branch target address cache | Rodney Wayne Smith, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2010-11-02 |
| 7805588 | Caching memory attribute indicators with cached memory data field | Jeffrey Todd Bridges, James Norris Dieffenderfer, Thomas Andrew Sartorius, Rodney Wayne Smith | 2010-09-28 |
| 7769983 | Caching instructions for a multiple-state processor | Rodney Wayne Smith | 2010-08-03 |
| 7716460 | Effective use of a BHT in processor having variable length instruction set execution modes | Rodney Wayne Smith | 2010-05-11 |
| 7711930 | Apparatus and method for decreasing the latency between instruction cache and a pipeline processor | James Norris Dieffenderfer, Richard W. Doing, Steven R. Testa, Kenichi Tsuchiya | 2010-05-04 |
| 7711927 | System, method and software to preload instructions from an instruction set other than one currently executing | Thomas Andrew Sartorius, Rodney Wayne Smith | 2010-05-04 |
| 7676659 | System, method and software to preload instructions from a variable-length instruction set with proper pre-decoding | Thomas Andrew Sartorius, Rodney Wayne Smith | 2010-03-09 |
| 7650466 | Method and apparatus for managing cache partitioning using a dynamic boundary | James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius, Rodney Wayne Smith, Robert Douglas Clancy +1 more | 2010-01-19 |
| 7617387 | Methods and system for resolving simultaneous predicted branch instructions | Rodney Wayne Smith, James Norris Dieffenderfer, Thomas Andrew Sartorius | 2009-11-10 |
| 7478228 | Apparatus for generating return address predictions for implicit and explicit subroutine calls | James Norris Dieffenderfer, Thomas Andrew Sartorius, Rodney Wayne Smith | 2009-01-13 |
| 7421568 | Power saving methods and apparatus to selectively enable cache bits based on known processor state | James Norris Dieffenderfer, Jeffrey Todd Bridges, Rodney Wayne Smith, Thomas Andrew Sartorius | 2008-09-02 |
| 7415638 | Pre-decode error handling via branch correction | Rodney Wayne Smith, James Norris Dieffenderfer, Jeffrey Todd Bridges, Thomas Andrew Sartorius | 2008-08-19 |
| 7406613 | Translation lookaside buffer (TLB) suppression for intra-page program counter relative or absolute address branch instructions | James Norris Dieffenderfer, Thomas Andrew Sartorius, Rodney Wayne Smith | 2008-07-29 |
| 7404042 | Handling cache miss in an instruction crossing a cache line boundary | Jeffrey Todd Bridges, Rodney Wayne Smith, Thomas Andrew Sartorius | 2008-07-22 |
| 7281120 | Apparatus and method for decreasing the latency between an instruction cache and a pipeline processor | James Norris Dieffenderfer, Richard W. Doing, Steven R. Testa, Kenichi Tsuchiya | 2007-10-09 |
| 7278012 | Method and apparatus for efficiently accessing first and second branch history tables to predict branch instructions | Thomas Andrew Sartorius, Jeffrey Todd Bridges, James Norris Dieffenderfer, Rodney Wayne Smith | 2007-10-02 |