AB

Alexander BURLAK

PR Proteantecs: 1 patents #11 of 12Top 95%
Overall (All Time): #2,602,924 of 4,157,543Top 65%
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Patent #TitleCo-InventorsDate
11740281 Integrated circuit degradation estimation and time-of-failure prediction using workload and margin sensing Eyal Fayneh, Edi Shmueli, Evelyn Landman, Inbar WEINTROB, Yahel DAVID +2 more 2023-08-29