Issued Patents All Time
Showing 26–50 of 50 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 11341397 | Computation of neural network node | Jung Ko, Steven Teig | 2022-05-24 |
| 11295200 | Time-multiplexed dot products for neural network inference circuit | Jung Ko, Steven Teig | 2022-04-05 |
| 11250326 | Splitting neural network filters for implementation by neural network inference circuit | Jung Ko, Steven Teig | 2022-02-15 |
| 11222257 | Non-dot product computations on neural network inference circuit | Jung Ko, Steven Teig | 2022-01-11 |
| 11210586 | Weight value decoder of neural network inference circuit | Jung Ko, Steven Teig | 2021-12-28 |
| 11205115 | Neural network inference circuit | Jung Ko, Steven Teig | 2021-12-21 |
| 11176450 | Three dimensional circuit implementing machine trained network | Steven Teig | 2021-11-16 |
| 11170289 | Computation of neural network node by neural network inference circuit | Jung Ko, Steven Teig | 2021-11-09 |
| 11157670 | Systems and methods for inter-die block level design | Javier A. Delacruz, Eric Nequist, Jung Ko | 2021-10-26 |
| 11152336 | 3D processor having stacked integrated circuit die | Steven Teig, Ilyas Mohammed, Javier A. Delacruz | 2021-10-19 |
| 11127738 | Back biasing of FD-SOI circuit blocks | Javier A. Delacruz, David Edward Fisch, Xu Chang, Liang Wang | 2021-09-21 |
| 11049013 | Encoding of weight values stored on neural network inference circuit | Jung Ko, Steven Teig | 2021-06-29 |
| 11003736 | Reduced dot product computation circuit | Jung Ko, Steven Teig | 2021-05-11 |
| 10977338 | Reduced-area circuit for dot product computation | Jung Ko, Steven Teig | 2021-04-13 |
| 10970627 | Time borrowing between layers of a three dimensional chip stack | Steven Teig, Javier A. Delacruz | 2021-04-06 |
| 10762420 | Self repairing neural network | Steven Teig | 2020-09-01 |
| 10740434 | Reduced dot product computation circuit | Jung Ko, Steven Teig | 2020-08-11 |
| 10719762 | Three dimensional chip structure implementing machine trained network | Steven Teig, Javier A. Delacruz | 2020-07-21 |
| 10672745 | 3D processor | Steven Teig, Ilyas Mohammed, Javier A. Delacruz | 2020-06-02 |
| 10672744 | 3D compute circuit with high density Z-axis interconnects | Steven Teig, Ilyas Mohammed, Javier A. Delacruz | 2020-06-02 |
| 10672743 | 3D Compute circuit with high density z-axis interconnects | Steven Teig, Ilyas Mohammed, Javier A. Delacruz | 2020-06-02 |
| 10664564 | Systems and methods for inter-die block level design | Javier A. Delacruz, Eric Nequist, Jung Ko | 2020-05-26 |
| 10607136 | Time borrowing between layers of a three dimensional chip stack | Steven Teig, Javier A. Delacruz | 2020-03-31 |
| 9940995 | Methods and apparatus for reusing lookup table random-access memory (LUTRAM) elements as configuration random-access memory (CRAM) elements | Trevis Chandler, Jung Ko, Dipak K. Sikdar | 2018-04-10 |
| 9916889 | Memory circuitry with row-wise gating capabilities | — | 2018-03-13 |