Issued Patents All Time
Showing 76–100 of 104 patents
| Patent # | Title | Co-Inventors | Date |
|---|---|---|---|
| 9748153 | Process for making and using a semiconductor wafer containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configure | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-08-29 |
| 9741741 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and GATECNT-short-configured, NCEM-enables fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-08-22 |
| 9741703 | Integrated circuit containing standard logic cells and ilbrary-compatible, NCEM-enabled fill cells, including at least via-open-configured, gate-short-configured, TS-short-configured, and AA-short-conigured, NCEM-enabled fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-08-22 |
| 9728553 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, GATE-short-configured, and TS-short-configured, NCEM-enabled fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-08-08 |
| 9721938 | Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including tip-to-tip short configured fill cells, and the second DOE including corner short configured fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-08-01 |
| 9721937 | Integrated circuit containing first and second does of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-tip short configured fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-08-01 |
| 9711496 | Integrated circuit containing first and second DOEs of standard cell compatible, NCEM-enabled fill cells, with the first DOE including side-to-side short configured fill cells, and the second DOE including tip-to-side short configured fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-07-18 |
| 9711421 | Process for making semiconductor dies, chips, and wafers using in-line measurements obtained from DOEs of GATE-snake-open-configured, NCEM-enabled fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-07-18 |
| 9691672 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and metal-short-configured, NCEM-enabled fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-06-27 |
| 9653446 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and AA-short-configured, NCEM-enabled fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-05-16 |
| 9646961 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, AACNT-short-configured, TS-short-configured, and metal-short-configured, NCEM-enabled fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-05-09 |
| 9627371 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and AA-short-configured, NCEM-enabled fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-04-18 |
| 9627370 | Integrated circuit containing standard logic cells and library-compatible, NCEM-enabled fill cells, including at least via-open-configured, GATE-short-configured, GATECNT-short-configured, and TS-short-configured, NCEM-enabled fill cells | Stephen Lam, Tomasz Brozek, Jeremy Cheng, Simone Comensoli, Indranil De +20 more | 2017-04-18 |
| 9496119 | E-beam inspection apparatus and method of using the same on various integrated circuit chips | Indranil De, Marian Mankos, Christopher Hess | 2016-11-15 |
| 7673262 | System and method for product yield prediction | Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis +4 more | 2010-03-02 |
| 7568180 | Generalization of the photo process window and its application to OPC test pattern design | Hans Eisenmann, Kai Peter, Jonathan O. Burrows, Yunqiang Zhang | 2009-07-28 |
| 7527987 | Fast localization of electrical failures on an integrated circuit system and method | Christopher Hess, Sherry Lee, Larg Weiland | 2009-05-05 |
| 7487474 | Designing an integrated circuit to improve yield using a variant design element | Joe Davis, Christopher Hess, Sherry Lee, Enrico Malavasi, Abdulmobeen Mohammad +9 more | 2009-02-03 |
| 7434197 | Method for improving mask layout and fabrication | Christoph Dolainsky, Jonathan O. Burrows, Joseph C. Davis, Rakesh Vallishayee, Howard Read +2 more | 2008-10-07 |
| 7395518 | Back end of line clone test vehicle | Christopher Hess | 2008-07-01 |
| 7373625 | System and method for product yield prediction | Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis +4 more | 2008-05-13 |
| 7356800 | System and method for product yield prediction | Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis +4 more | 2008-04-08 |
| 7348594 | Test structures and models for estimating the yield impact of dishing and/or voids | Brian E. Stine, Yanwen Fei | 2008-03-25 |
| 7197726 | Test structures for estimating dishing and erosion effects in copper damascene technology | Markus Decker, Christopher Hess, Brian E. Stine, Larg Weiland | 2007-03-27 |
| 7174521 | System and method for product yield prediction | Brian E. Stine, Christopher Hess, John Kibarian, Kimon Michaels, Joseph C. Davis +4 more | 2007-02-06 |