{"@context": "https://schema.org", "@type": "BreadcrumbList", "itemListElement": [{"@type": "ListItem", "position": 1, "name": "Home", "item": "https://www.patentleaderboard.com/"}, {"@type": "ListItem", "position": 2, "name": "Multicore bus architecture with non-blocking high performance transaction credit system", "item": "https://www.patentleaderboard.com/patent/9904645"}]}
Patent Leaderboard
USPTO Patent Rankings Data through Dec 31, 2025
Home › Multicore bus architecture with non-blocking high performance transaction credit system

Multicore bus architecture with non-blocking high performance transaction credit system

US Patent 9904645 · Granted Feb 27, 2018

Estimated economic value: $23,171,000 ⓘ

Assignee

Inventors

View full patent text on Google Patents →

More Patents by These Inventors

Pipelined read-modify-write operations in cache memory2025
Register file structures combining vector and scalar data with global and local 2025
Register file structures combining vector and scalar data with global and local 2025
Write control for read-modify-write operations in cache memory2025
Write control for read-modify-write operations in cache memory2025
Vector maximum and minimum with indexing2025
Method and apparatus for implied bit handling in floating point multiplication2025
Streaming engine with early exit from loop levels supporting early exit loops an2025
Converting a stream of data using a lookaside buffer2025
Controller with caching and non-caching modes2025
Controller with caching and non-caching modes2025
System and method to control the number of active vector lanes in a processor2025